Semiconductor device, manufacturing method thereof, and electronic device
A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electric solid state devices, circuits, etc., can solve the problems affecting the final performance of the device, and achieve the effect of good device performance, device profile, good yield and performance
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Embodiment 1
[0040] The following will refer to Figure 4A ~ Figure 4E A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.
[0041] First, if Figure 4A As shown, a semiconductor substrate 400 is provided, the semiconductor substrate 400 includes a dense region and a sparse region, and a gate stack is formed on the semiconductor substrate 400, and the gate stack includes a tunnel oxide layer 401, Floating gate 402, gate dielectric layer 403, control gate 404, and control gate hard mask layer 405, on which a hard mask layer 406, an etching stop layer 407, and a word line pattern layer 408 are sequentially formed , a first filling layer 409 , a first anti-reflection layer 410 and a patterned first photoresist layer 411 .
[0042] Wherein, the semiconductor substrate 400 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also i...
Embodiment 2
[0070] The present invention also provides a semiconductor device fabricated by the above method, such as Figure 5 As shown, the semiconductor device includes: a semiconductor substrate 500, on which a word line WL and a selection gate SG are formed, and the word line WL and the selection gate SG include a tunnel oxide layer 501, a floating gate 502, The stacked structure of the gate dielectric layer 503 , the control gate 504 and the control gate hard mask layer 505 .
[0071] Wherein, the semiconductor substrate 500 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconductors. The layer structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and / or PMOS, can...
Embodiment 3
[0075] Still another embodiment of the present invention provides an electronic device, including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a semi-semiconductor substrate, on which a word line and a selection gate are formed, and the word line and the selection gate include a tunnel oxide layer, a floating gate, a gate dielectric layer, a control Gate and control gate hard mask layer stack structure.
[0076] The semiconductor substrate can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors etc. or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and / or PMOS, can be formed on the semiconductor su...
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