A method for forming a channel layer in a channel hole

Abstract

The invention provides a channel hole internal channel layer forming method. According to the channel hole internal channel layer forming method, during sedimentation of polycrystalline silicon, whenreaction gas is silane, the temperature range inside the reacting furnace is 480-550 DEG C, and the pressure range inside the reacting furnace is 0.45-1 T, so that, at the relatively low temperature and relatively high pressure, the amount of gas inside the reacting furnace can be increased, density uniformity of gas on the same plane can be similar, and further uniform growth thickness and deviceperformance improvement can be achieved.

Description

technical field [0001] The invention relates to the field of 3D NAND devices and its manufacture, in particular to a method for forming a channel layer in a channel hole. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, a stacked 3D NAND memory structure is realized by vertically stacking multiple layers of data storage units. When forming a 3D NAND memory, first, a silicon nitride (SiN) layer and a silicon oxide (SiO 2 ) layer stacking layer; then, a channel hole (Channel hole) is formed in the stacking layer, and the channe...

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Problems solved by technology

[0004] When etching to form channel holes, it is hoped that the upper and lower parts can form concentric circles, but in the actual process, due to the deep hole depth and the limitation of the process, it is impossible to make the upper and lower concentric circles, and the upper part can basically guarantee concentricity. round, and the lower part is basically elliptical, which causes the thickness non-uniformity of the channel layer of polysilicon when it is formed

refer to figure 1 Shown is the SEM (scanning electron microscope) photograph of the cross-section of the channel hole bottom. It can be seen that the bottom of the channel hole is in the shape of an ellipse, and the thickness distribution of polysilicon is uneven. The thickness of polysilicon in the part of the long axis of the ellipse is The thickness B of the shorter axis part of A is much larger, which will affect the electrical properties such as channel current, subthreshold slope, and electric field intensity distribution, and affect the overall performance of the device

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