VLSI (Very Large Scale Integration) design method of fast Fourier transform (FFT)

Abstract

The invention relates to a VLSI (Very Large Scale Integration) design method of a fast Fourier transform (FFT). An adopted 16-point FFT hardware architecture includes four improved butterfly computation modules, one complex-number multiplication module, four delay storage modules, two imaginary-part multiplication modules and one counter control module, and is divided into four levels. Each levelhas one of the improved butterfly computation modules and one of the delay storage modules. The complex-number multiplication module is located between the second level and the third level. One of theimaginary-part multiplication modules is located between the first level and the second level, and the other imaginary-part multiplication module is located between the third level and the fourth level. An effect of the counter control module is to control all the above modules to work normally. According to the improved butterfly computation modules, circuit structures that "adders are before selectors" in butterfly computation modules are improved into butterfly computation circuit structures that "the selectors are before the adders". Key-path delay of the improved butterfly computation circuit structures is unchanged.

Description

technical field [0001] The present invention belongs to the category of VLSI (Very Large Scale Integration, referred to as VLSI) design, and designs a high-performance Fast Fourier Transform (Fast Fourier Transform, referred to as FFT) VLSI structure. Background technique [0002] Fast Fourier Transform (FFT) is a fast implementation of Discrete Fourier Transform (DFT). It is one of the important algorithms in modern digital signal processing and is widely used in OFDM modulation, GPS signal acquisition, radar imaging and digital communication, etc. field. Due to the large amount of FFT calculation, in order to meet the needs of real-time processing, hardware circuits must be used to improve the calculation speed. Therefore, it is of great significance to design an efficient fast Fourier transform hardware structure. Among them, improving system performance and reducing hardware overhead have become the main considerations in the optimal design of fast Fourier transform ar...

AI Technical Summary

Problems solved by technology

In the paper "Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs", Bin Zhou et al. used the method of formula transformation to reduce the four real multipliers in the complex multiplier to three. The hardware overhead is still large, and the calculation speed is also very low. , so the hardware efficiency is very low

Bin Zhou improved the complex multiplier in the paper "Pipeline FFTarchitectures optimized for FPGAs". On the basis of the formula transformation method, the complex multiplier unit is realized by using the DSP module. Although the calculation speed has been improved to a certain extent, the hardware overhead is relatively large. Therefore, the hardware efficiency is low

In the paper "A Modified Pipeline FFT Architecture", Hung Yu Wang et al. used a CSD constant multiplier to replace the traditional complex multiplier, and also omitted the ROM storage unit. Although the hardware overhead was greatly saved, the calculation speed was still not high. lead to less efficient hardware

Ze Ke Wang et al. proposed a pipeline structure combining SDF and SDC in the paper "A CombinedSDC-SDF Architecture for Normal I / O Pipelined Radix-2FFT", which can time-division multiplex multipliers and adders, and the calculation speed is Great improvement, but the hardware resource overhead is large, so the hardware efficiency is low

[0004] Based on the above analysis, the existing FFT architecture ignores the impact of the circuit structure of the dish-shaped computing module on the layout and wiring, resulting in a large hardware overhead for the overall architecture; in addition, the circuit structure of the complex multiplier for the twiddle factor is complex, and the critical path is long, resulting in FFT calculation speed Slower, which eventually leads to inefficient FFT overall architecture hardware

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