Adaptive chip and configuration method

A self-adaptive, chip technology, applied in special data processing applications, logic circuits, instruments, etc., can solve problems such as speed limitation, huge data volume, and FPGA cannot be reconfigured, achieving the effect of low power consumption and low cost

Active Publication Date: 2018-08-21
吴国盛 +1
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Even if partial reconfiguration can be achieved, due to the huge amount of configured data, the speed of reconfiguration is greatly limited, so FPGA cannot achieve ultra-fast reconfiguration
[0007] With the increase of chip size and design complexity, chip reconfiguration time is getting longer and longer, it is difficult to use existing FPGA technology to achieve dynamic real-time reconfiguration

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Adaptive chip and configuration method
  • Adaptive chip and configuration method
  • Adaptive chip and configuration method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus their repeated descriptions will be omitted.

[0056] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or mo...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

An adaptive chip (100) and configuration method, comprising: a plurality of dynamically reconfigurable units (110), arranged in the form of an array, each dynamically reconfigurable unit (110) can be dynamically reconfigured to different operations as required function and / or input and output functions, wherein each dynamically reconfigurable unit (110) is connected to a plurality of adjacent dynamically reconfigurable units (110), and from the plurality of adjacent dynamically reconfigurable units ( One or more of 110) obtains data, and outputs an operation result based on the data to at least one adjacent dynamically reconfigurable unit (110). Can reduce costs.

Description

technical field [0001] The disclosure relates to a chip and an electronic device, in particular to an adaptive chip, a configuration method thereof, and an electronic device with the adaptive chip. Background technique [0002] The development of science and technology has put forward higher and higher requirements for chip design and manufacturing. The use of system-on-chip (SoC) supported by IP core multiplexing and software-hardware co-verification has become the mainstream method of high-performance integrated circuit design. . From chip system definition, front-end circuit design, back-end physical implementation, chip manufacturing, packaging and testing to software development and finally mass production has also evolved into a huge system engineering. At present, the mainstream chips are still ASIC and FPGA chips. [0003] ASIC is an integrated circuit designed and manufactured in response to specific user requirements and the needs of specific electronic systems. ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F15/177
CPCH03K19/17728H03K19/1774H03K19/17752G06F15/7867G06F30/34G06F15/177G06F7/57
Inventor 吴国盛
Owner 吴国盛
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap