A duty ratio adjustment circuit and its realization method

Abstract

The invention discloses a duty ratio adjusting circuit and an implementation method thereof. The duty ratio adjusting circuit comprises a DC bias voltage adjusting circuit used for converting a digitalized input clock signal CLK _ in into a DC bias voltage controlled clock; a phase inverter used for converting the DC bias voltage controlled clock into a digitalized clock signal CLK _ out; a control voltage generation circuit used for generating a control voltage under the control of high and low levels of the output clock signal CLK _ out, wherein the control voltage is connected to the DC bias voltage adjusting circuit to adjust the DC bias voltage of the DC bias voltage controlled clock output by the DC bias voltage adjusting circuit. By adoption of the duty ratio adjusting circuit, the duty ratio adjusting circuit capable of adjusting the duty ratio of signals to 50% is realized.

Description

technical field [0001] The invention relates to an adjusting circuit and its realization method, in particular to a duty ratio adjustment circuit and its realization method. Background technique [0002] In modern integrated circuits, a 50% duty cycle clock plays a vital role. However, in actual circuits, many reasons will cause the clock duty cycle to deviate from 50%. For example, due to the difference in driving capability between PMOS and NMOS, and the difference in the distribution of interconnect parasitic capacitance, it is difficult for the oscillator circuit to output a 50% duty cycle. than signal. [0003] It can be seen that the existing duty ratio adjustments are either poor in resistance to voltage and temperature changes, or the design is relatively complicated, so how to generate a 50% duty ratio clock suitable for high-speed circuit systems has become a hot issue that needs to be solved urgently. [0004] Therefore, it is really necessary to provide a duty ...

AI Technical Summary

Problems solved by technology

However, in actual circuits, many reasons will cause the clock duty cycle to deviate from 50%. For example, due to the difference in driving capability between PMOS and NMOS, and the difference in the distribution of interconnect parasitic capacitance, it is difficult for the oscillator circuit to output a 50% duty cycle. ratio signal

[0003] It can be seen that the existing duty cycle regulation is either poor in resistance to voltage and temperature changes, or the design is relatively complicated, so how to generate a 50% duty cycle clock suitable for high-speed circuit systems has become a hot issue that needs to be solved urgently

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