Storage, formation method thereof and semiconductor device

Abstract

The invention provides a storage, a formation method thereof and a semiconductor device. A first isolation line covering a word line in a self-alignment way is used as a first isolation screen, a second isolation line covering the word line in a self-alignment way is utilized so that the second isolation line is combined with the word line to form a second isolation screen, and a contact window corresponding to a second contact area is defined by intersection of the first isolation screen and the second isolation screen. The contact window in contact with a corresponding storage node can be defined without a photoetching process, the fabrication cost is reduced, the alignment deviation among multiple steps of the photoetching process also can be reduced, and the contact resistance between the storage node formed subsequently and the second contact area is favorably improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a memory, a method for forming the same, and a semiconductor device. Background technique [0002] A memory typically includes a storage capacitor for storing charge representing stored information and a storage transistor connected to the storage element. An active region, a drain region and a gate are formed in the memory transistor, the gate is used to control the flow of current between the source region and the drain region, and is connected to a word line conductor, and the source region is used to form The bit line contact area is used to connect to the bit line, and the drain area is used to form a storage node contact area to be connected to the storage capacitor. [0003] In the preparation method of traditional memory, generally include defining active area (Active Area, AA), defining word line conductor (Word Line, WL), defining bit line contact window, defini...

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Problems solved by technology

[0004] With the continuous reduction of the size of the memory, the feature size of each component in the memory (for example, the line width of the word line conductor and the bit line, the opening size of the contact window, etc.) will be a great challenge

Moreover, when performing a multi-pass photolithography process, there is a problem of alignment deviation between different masks, so that after the multi-pass masks are superimposed on each other, the multiple displacement deviations of the corresponding multi-pass masks will be superimposed on each other, which will further affect the The electrical connection between some components in the memory affects the

Therefore, when the contact window of the storage node is directly defined by the photolithography process, a large displacement deviation will be generated between the formed storage node contact and the storage node contact area, and the contact resistance will be too large.

[0005] It can be seen that when the contact window corresponding to the contact area of ​​the storage node is directly defined by using the photolithography process to prepare the storage node contact, it is not only a problem of high manufacturing cost, but also the alignment accuracy of the multi-pass photolithography process is limited. , so that when multiple masks are superimposed on each other, a greater displacement deviation will occur

In this way, not only will the performance of the memory formed subsequently be affected, but it is also not conducive to the reduction of the size of the components.

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