An emif interface and ahb/apb timing bridge circuit and its control method

Abstract

The invention discloses a bridge circuit for an EMIF interface and an AHB / APB time series and a control method of the bridge circuit. The bridge circuit is connected with an external DSP through the EMIF interface, and comprises a DSP signal synchronization module, a DSP operation detection module, an address mapping controller, a data bit width matcher, an AHB / APB time series generation state machine and a configuration register. The bridge circuit is integrated in a SoC, and is connected with the external DSP through the EMIF interface to achieve the functions of analyzing, splicing and converting DSP access time series, and then finally realize the efficient operation for on-chip resources. The bridge circuit can support the access control, for 16 paths of AHB / APB slaves, of the DSP at most.

Description

technical field [0001] The invention belongs to the field of digital integrated circuits, and relates to an EMIF interface and AHB / APB timing bridge circuit and a control method thereof. The circuit is used in the field of SoC / embedded processor design with an EMIF control interface. Background technique [0002] The system on chip has the characteristics of miniaturization, low power consumption, and rich interfaces. In recent years, it has gradually become the control core of computer systems. However, because most of them use RISC processors as the core, their computing power is limited; in computer systems, in order to achieve efficient computing power , Often use the dual-core system of DSP+SoC. SoC is responsible for communication and control functions, and sends the data sent and received by the communication interface to DSP, and the data communication between DSP and SoC can be carried out through the dual-port buffer for data calculation. However, in this communic...

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Problems solved by technology

In the patent "A bus bridge between DCR bus and APB bus" (application number: 201410490661.7), a bridge circuit for converting from DCR to APB bus is described; in the patent "EMIF read and write timing of DSP and FPGA's AVALON Read and Write Timing Conversion Method" (application number: 201510188013.0) describes the conversion method between the EMIF read and write timing of DSP and the AVALON bus timing of FPGA, and the EMIF timing of DSP and AHB / APB of AMBA bus At present, there is no relevant research on the conversion method of time series

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