Method, device and system for scheduling memory access command

Abstract

The invention provides a method, a device and a system for scheduling a memory access command. The method comprises the steps: a memory controller receives a to-be-scheduled memory access command sent by memory access equipment, wherein the to-be-scheduled memory access command includes an original priority of the to-be-scheduled memory access command; the memory controller inserts the to-be-scheduled memory access command into a scheduling queue according to the relation between existing memory access commands in the scheduling queue, the relation between the to-be-scheduled memory access command and the existing memory access commands in the scheduling queue and the relation between the original priority of the to-be-scheduled memory access command and a current priority of the existing memory access commands in the scheduling queue. Therefore, memory access bandwidths and memory access delays of different memory access equipment can be satisfied, the operational stability of a computer system is improved, the idleness rate of a memory bus of the computer system is decreased, the bandwidth utilization rate is improved and the average memory access delay is reduced.

Description

technical field [0001] The present invention relates to computer technology, in particular to a memory access command scheduling method, device and system. Background technique [0002] The storage system in the computer system mostly uses Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM for short) equipment as the main memory (that is, memory), and the main memory and the central processing unit (Central Processing Unit; Abbreviation: CPU), graphics card, Gigabit Ethernet card and other memory access devices are connected through the memory controller. The memory controller receives the memory access command from the memory access device, then converts it into an operation command for the memory, and returns data for the read command or returns a response for the write command to the request source. All memory operations need to comply with strict timing specifications, and the delay caused by reading and writing memory operations to meet the timing spec...

AI Technical Summary

Problems solved by technology

[0005] However, in the above-mentioned technologies, the scheduling of memory access commands is not considered comprehensively, and the requirements for memory access bandwidth and memory access delay of some memory access devices cannot be guaranteed, which will cause the computer system to fail to work normally.

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