High-precision multi-phase clock correcting circuit

Abstract

The invention discloses a high-precision multi-phase clock correcting circuit, belonging to the field of analog integrated circuit technology, and particularly relating to a multi-phase clock phase error correction circuit. The high-precision multi-phase clock correcting circuit disclosed by the invention aims to solve the problem that the existing traditional multi-phase clock generator has clock delay errors due to non-ideal effects; a traditional multi-phase clock generation circuit generates a multi-phase clock by using a multi-level delay chain, and errors are caused by the mismatch between the delay units; and the high-precision multi-phase clock correcting circuit is beneficial to reduce the power consumption and save the chip area, is high in clock phase detection precision and easy to implement, is high in adjustment precision of the clock delay units, adopts the code values of digital codes to correspond to the delay size, ensures that the clock accuracy of the clock correction module depends on the feedback adjustment accuracy and the detection accuracy of the clock phase errors, and ensures that the high-precision multi-phase clock can be achieved.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, in particular to a multiphase clock phase error correction circuit. Background technique [0002] The traditional multi-phase clock generator is implemented by a delay-locked loop (Delay-Locked Loop, DLL). By comparing the phases of the reference clock and the feedback clock, the loop is locked, thereby outputting clock signals with multiple equal phases. In theory, the phase The number can be very large, and the phase difference is equal and constant. But in reality, due to the influence of non-ideal effects such as delay unit mismatch, transmission path mismatch, temperature change, and chip local stress difference, the difference between multi-phase clocks is unequal, and time mismatch occurs. [0003] In order to realize a high-precision multi-phase clock, the number of delay units in the delay line can be increased to strengthen the matching between delay units. This meth...

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Problems solved by technology

But in reality, due to the influence of non-ideal effects such as delay unit mismatch, transmission path mismatch, temperature change, and chip local stress difference, the difference between multi-phase clocks is unequal, and time mismatch occurs.

[0003] In order to realize a high-precision multi-phase clock, the number of delay units in the delay line can be increased to strengthen the matching between delay units. This method can effectively reduce the phase error and time mismatch, but it increases the circuit scale and system overhead. , and this method depends on the manufacturing level of the process, and is greatly affected by the application environment and temperature

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