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Packaging method for packaging structure integrated with power transmission chip

A technology of power transmission and packaging structure, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of the small number of different voltage rails available, the low power transmission efficiency of the power transmission system, etc., to reduce the design margin and improve the power transmission. Efficiency, the effect of improving response time

Active Publication Date: 2018-10-19
SJ SEMICON JIANGYIN CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a packaging method for a packaging structure integrated with a power transmission chip, which is used to solve the problem of low power transmission efficiency and the availability of different voltage rails in the existing power transmission system. less problem

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  • Packaging method for packaging structure integrated with power transmission chip
  • Packaging method for packaging structure integrated with power transmission chip
  • Packaging method for packaging structure integrated with power transmission chip

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Embodiment Construction

[0067] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0068] see Figure 1 to Figure 11 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed ar...

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Abstract

The present invention provides a packaging method for a packaging structure integrated with a power transmission chip. The packaging structure includes a power consumption chip and a power transmission chip connected under the power consumption chip; the power transmission chip is used to integrate an external power supply The voltage is converted into multiple voltages required by the power chip, and multiple power supply rails are provided for connecting the power chip. The packaging method of the present invention utilizes the power transmission chip 3 as an active 2.5D interposer, and integrates the power consumption chip 5 on the active 2.5D interposer through micro-bumps or other bump structures to obtain a three-dimensional stacked chip structure. The power transmission system of the entire system circuit board is realized by the power transmission chip, which can eliminate the parasitic resistance on the packaging substrate, thereby improving the power transmission efficiency, improving the response time of power control, and improving the fidelity.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and relates to a packaging method for a packaging structure integrated with a power transmission chip. Background technique [0002] All computing and communication systems require power delivery systems. A power delivery system converts the high voltage of a power supply to the many different low voltages required by the discrete components in the system. The efficiency of the power delivery system determines the power loss for down conversion, while the number of power delivery rails determines the number of discrete voltage supplies or devices that can be supported. [0003] Current power transfer technologies face the following challenges: [0004] 1. As the process node shrinks and the device voltage decreases, the efficiency of power transmission will decrease accordingly, resulting in greater power consumption. [0005] Second, adding more power transmission tracks requi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L21/77
CPCH01L21/56H01L21/77H01L2027/11892H01L2924/18161H01L2924/18162H01L2924/19105H01L21/568H01L2224/04105H01L2224/16225H01L2224/16227H01L2224/19H01L2224/73204H01L2224/82001
Inventor 林章申林正忠何志宏汤红
Owner SJ SEMICON JIANGYIN CORP
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