Chemical mechanical grinding method

Abstract

The scheme provides a chemical mechanical grinding method. After an oxide layer is deposited in a peripheral circuit region and a storage region of a three-dimensional storage, the peripheral circuit region is subjected to etching for the first time to enable the lowest height of the oxide layer in the peripheral circuit region to be equivalent to the highest height of the stage in the storage region; a barrier layer is formed on the oxide layer of the three-dimensional storage; then the storage region is subjected to etching for the second time, and the barrier layer and the oxide layer in the three-dimensional storage are subjected to chemical and mechanical grinding at the same time until the lowest height of the oxide layer, corresponding to the stage region, in the storage region is equivalent to the highest height of the stage; and next, the residual barrier layer in the three-dimensional storage is removed. Therefore, the barrier layer is formed on the surface of the oxide layer; and in addition, the removing speed of the barrier layer is slower than that of the oxide layer, so that the additional barrier layer can protect the structure of the storage region, Dishing defect influence in the prior art can be avoided, the overall technological uniformity of the three-dimensional storage can be improved, and the yield is improved.

Description

technical field [0001] The invention relates to the field of flash memory, and more specifically, relates to a chemical mechanical grinding method. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, a stacked 3D NAND memory structure is realized by vertically stacking multi-layer data storage units. These vertically stacked multi-layer data storage units are called steps. However, in the process of making the steps, after the steps are formed, a large step height difference will be formed between the uppermost layer and the lowe...

AI Technical Summary

Problems solved by technology

However, the inventors have found that, due to the poor stability of the CMP process, the storage area is often affected by recessed defects, and the structure is damaged, such as image 3 As shown, this will directly affect the uniformity of subsequent CH (channel hole, channel process), GL (gate line, gate control line process), CT (contact, connection hole process) and BEOL (back-end metal connection process)

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