Method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of FPGA

Abstract

The invention discloses a method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of an FPGA. The method comprises the steps that 1, functions of a quasi-Newton algorithm are analyzed, and main calculation modules of the quasi-Newton algorithm are divided; 2, advanced languages C and C++ are utilized to achieve modules in the step 1, and the correctness of the functions of the algorithm are verified; 3, the quasi-Newton algorithm with the functions correct through function verification in the step 2 serves as an input file, a high-level synthesis tool is utilized to convert the advanced languages into RTL-level languages, and generated RTL codes are verified; 4, the generated RTL codes are manufactured into bitstream files, and the files are downloaded to the configurable logical parts of the FPGA. Starting from the quasi-Newton algorithm acceleration, high-level synthesis is utilized to achieve the quasi-Newton algorithm, quasi-Newton algorithm acceleration is achieved through the FPGA, and the FPGA development difficulty is reduced.

Description

technical field [0001] The present invention relates to a quasi-Newton algorithm (Quasi-Newton, QN) acceleration technology, in particular to a high-level synthesis (High Level Synthesis, HLS) tool optimization acceleration quasi-Newton algorithm based on field programmable gate arrays (Field Programmable Gate Arrays, FPGA) Methods. Background technique [0002] The quasi-Newton algorithm is the most effective method for solving nonlinear optimization, and it is widely used in various fields, such as stochastic optimization, integrated circuit layout and loading frequency control of power systems. A critical factor for these applications is obtaining an optimal solution within a limited time. However, the quasi-Newton algorithm takes a lot of time because it contains a large number of iterative algorithms. Therefore, the acceleration of the quasi-Newton algorithm is an important research direction. [0003] With the rapid development of FPGA, the current FPGA platform has...

AI Technical Summary

Problems solved by technology

Complicated timing design inside the FPGA generally requires state machine development, which takes a lot of time for analysis and design, and software engineers use high-level languages ​​​​C, C++ for development and hardware engineers use RTL design language to design circuits. There is a certain gap in background knowledge

This leads to the development of FPGA is very different from the development of traditional single-chip microcomputer, and the development is more difficult (see literature [4])

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