Heterogeneous multi-core processor power consumption control device and method

Abstract

The invention relates to a heterogeneous multi-core processor power consumption control device and method. The device comprises n CPUs and m IPs, and further comprises a clock management unit, a power source management unit and a clock control unit, wherein n and m are integers larger than 1. The power source management unit comprises m power source interfaces which control power sources of the connected IPs to be switched on or off respectively according to control commands of the clock management unit. The clock control unit comprises n+m clock gating modules, and each clock gating module is connected with one CPU or one IP, and the clock gating modules control clocks of the connected CPUs or the IPs to be switched on or off respectively according to control commands of the clock management unit. Each CPU can control the clock management unit to send the control commands to any power source interface or any clock gating clock module. By means of the scheme, power consumption of a chip and design difficulty of the chip can be reduced.

Description

technical field [0001] The present invention relates to the technical field of multi-core systems, in particular to a device for controlling power consumption of heterogeneous multi-core processors and a method for controlling power consumption thereof. Background technique [0002] With the improvement of integrated circuit design level and manufacturing process, chip performance and integration are getting higher and higher. Many new chips use multiple cores to increase performance, which greatly increases chip power consumption. In order to control chip power consumption, many chips adopt the design of large and small cores. When performance is prioritized, large and small cores are used for work, and only small cores are used in low power consumption mode to reduce power consumption. [0003] Each core of a multi-core system has a different function, and they are not necessarily in working state at the same time. Using this characteristic of the chip, power consumption m...

AI Technical Summary

Problems solved by technology

Such an operation method increases additional power consumption. At the same time, with the increase of core processors, the inter-core communication mechanism is complicated, and the chip bus design is complicated, which increases the difficulty of chip design.

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