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Multi-ADC high-speed crossing sampling calibration device and method

A calibration device and calibration method technology, applied in the direction of analog/digital conversion calibration/testing, electrical components, code conversion, etc., can solve the problems of reconstruction waveform distortion, jitter increase, and the reduction of the analog bandwidth of the whole machine, so as to improve the calibration efficiency , the effect of reducing the uncertainty problem

Active Publication Date: 2017-04-26
THE 41ST INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Due to the differences in the phase, offset, and gain of multiple ADCs, the difference is greater with temperature changes. If calibration is not performed, the performance indicators of the signal will be deteriorated after data reorganization, resulting in distortion of the reconstructed waveform, which reduces the analog bandwidth of the whole machine. The jitter becomes larger

Method used

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  • Multi-ADC high-speed crossing sampling calibration device and method
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  • Multi-ADC high-speed crossing sampling calibration device and method

Examples

Experimental program
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Embodiment 1

[0039] combine Figure 1 to Figure 7 , a multi-ADC high-speed cross-sampling calibration device, including a channel input selection module, the channel input selection module is connected with a signal conditioning circuit, the signal conditioning circuit is connected with a driving circuit, and the driving circuit is respectively connected with a phase calibration circuit, a gain calibration circuit and an offset The calibration circuit, the phase calibration circuit, the gain calibration circuit and the offset calibration circuit are all connected with a high sampling rate ADC module, and the high sampling rate ADC module is connected with an FPGA, and the FPGA is a field programmable gate array, wherein the high sampling rate ADC module includes Four high sampling rate ADC chips.

[0040]The phase calibration circuit includes a sampling clock system. The sampling clock system outputs four 1.25GHz sampling clocks. The four 1.25GHz sampling clocks are respectively connected ...

Embodiment 2

[0044] The calibration method of a multi-ADC high-speed cross-sampling calibration device in the above-mentioned embodiment 1 includes a phase calibration method, a gain calibration method and an offset calibration method.

[0045] Among them, the phase calibration method uses DDR clock sampling, and outputs four-phase 1.25GHz sampling clocks with a difference of 45 degrees. One channel is used as the reference, and the other three channels are respectively connected with delay regulators to adjust the delay time, so that the clock difference between two adjacent channels is 100 ps, ​​and the four ADCs are alternately sampled to obtain an equivalent sampling rate of 10GSa / s. Use the first frequency-divided clock as the interpolation clock, and solve the problem of high-precision testing by amplifying the difference twice. The phase measurement results are used for coarse adjustment and fine adjustment. The coarse adjustment adjusts the delay regulator, and the fine adjustment a...

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Abstract

The invention provides a multi-ADC high-speed crossing sampling calibration device and method, and the method comprises the steps: phase calibration, gain calibration and offset calibration. The phase calibration mainly solves a delay consistency problem of sampling clocks, the gain calibration mainly solves an amplitude consistency of four signals and the offset calibration mainly solves an offset consistency problem of four signals. Through the calibration of the phase, gain and offset of four-way ADCs with the 2.5 GSa / s sampling rate, the device and method enable the sampling rate of the four ADCs to reach 10 GSa / s during crossing sampling. Moreover, the waveform does not have distortion after data recombination, and the performance indexes meet the ideal requirements. A whole testing calibration control circuit is implemented through upper computer software and an FPGA. After calibration, the phase, gain and offset are guaranteed to be consistent, and a calibration result is complemented during collection display, thereby enabling the phase difference of four collection clocks to be 100ps, and enabling the gain and offset to be equal.

Description

technical field [0001] The invention relates to the field of signal acquisition, in particular to a multi-ADC high-speed cross-sampling calibration device and a calibration method. Background technique [0002] The multi-ADC high-speed cross-sampling technology mainly calibrates the phase, offset, and gain of multiple ADCs to increase the sampling rate from the current 2.5GSa / s sampling rate of a single ADC to the entire system sampling rate to 10GSa / s. Due to the differences in the phase, offset, and gain of multiple ADCs, the difference is greater with temperature changes. If calibration is not performed, the performance indicators of the signal will be deteriorated after data reorganization, resulting in distortion of the reconstructed waveform, which reduces the analog bandwidth of the whole machine. The jitter becomes larger. Contents of the invention [0003] The first purpose of the present invention is to provide a multi-ADC high-speed cross-sampling calibration d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1009
Inventor 栗永强张永坡布乃红戚瑞民杨小光李雷彭海军王俊生
Owner THE 41ST INST OF CHINA ELECTRONICS TECH GRP
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