FPGA-based high-speed adaptive DVB-S2 LDPC decoder and decoding method

Abstract

The invention relates to an FPGA-based high-speed adaptive DVB-S2 LDPC decoder and a decoding method. the method comprises steps: (1) matrix transformation is carried out, the generated left matrix has a quasi-cyclic structure, and the right matrix is a new matrix for a triangle-to-dual-diagonal (RTS) sub matrix; (2) RAM and iteration times are initialized; (3) the two parts of matrixes complete variable node information updating and data write back; (4) node information updating and write back are verified, a syndrome vector s is calculated, and one is added to the iteration times iter; (5) if the syndrome vector s is equal to 0 or the maximum iteration times are reached, a sixth step is carried out, or otherwise, the third step is carried out for next-round iteration processing; and (6) a decoding judgment bit is read, and a decoding codeword is outputted.

Description

technical field [0001] The invention relates to an adaptive LDPC decoder technology conforming to the DVB-S2 standard, in particular to an FPGA-based high-speed adaptive DVB-S2 LDPC decoder and a decoding method. Background technique [0002] The second generation of European Digital Satellite Television Broadcasting (DVB-S2) standard provides a high-power and high-spectrum-efficient adaptive coding and modulation scheme, which has been widely used in satellite broadcasting television systems. In order to apply this efficient adaptive coding and modulation scheme to earth exploration satellites, in 2013, the International Space Data System (CCSDS) 131.3-B-1 standard (CCSDS space link protocols over ETSI dvb-s2 standardCCSDS 131.3-b- 1, blue book, march 2013) provides a technical solution for using DVB-S2 standard to transmit CCSDS transmission frames, which solves the format compatibility problem between DVB-S2 and CCSDS. [0003] However, since the maximum transmission rat...

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Problems solved by technology

However, some other decoder implementations can achieve higher decoding throughput, but the design itself is only designed for the matrix of a single code rate in the standard, and the decoder does not actually have the adaptive ability of code rate compatibility. , such as: literature (Seok-Min Kim, Chang-Soo Park, and Sun-Young Hwang, "A Novel Partially Parallel Architecture for High-throughput LDPCDecoder for DVB-S2," IEEE Trans.Consumer Electronics, Vol.56, No. 2, May 2010) designed a module B / CFM with both variable node and check node functions, and the maximum throughput of the DVB-S2 LDPC decoder can reach 1020Mbps; literature (Tae Hun Kim, Tae Doo Park, Gun Yeol Park, Hae ChanKwon, Ji Won Jung, "High Throughput LDPC Decoder Architecture for DVB-S2," ICUFN2013, pp430-434) adopted the HSS strategy and simple check node update algorithm, and adopted the architecture to save storage resources to achieve the fixed Bit rate decoder, the throughput can exceed 2Gbps

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