Chip package structure and method

Abstract

The embodiment of the invention discloses a chip package structure and method. The chip package structure and method can reduce the thickness of the package structure, improve the density of a base pin, add the number of the interconnection channels and increase the bandwidth of the top chip. The chip package structure comprises: a redistribution layer (RDL); a target chip including a source surface and a back surface, wherein the source surface of the target chip is connected with the first surface of the RDL; a substrate, wherein the first surface of the substrate is opposite to the back of the target chip; and an interconnection channel located around the target chip, one end of the interconnection channel is connected with the first surface of the RDL, and the other end of the interconnection channel is connected with the first surface of the substrate.

Description

technical field [0001] The present application relates to the field of chip packaging, and more particularly, to chip packaging structures and methods. Background technique [0002] With the rapid growth of portable electronic products, semiconductor packages mounted on printed circuit boards (Printed Circuit Broad, "PCB" for short) in electronic devices are gradually becoming smaller and thinner. Therefore, the position of packaging in the industry chain has become more important. [0003] At present, there is a known packaging structure, which adopts a package on package (Package on Package, referred to as "POP") technology to package a chip between an upper and a lower substrate. Specifically, the lower substrate can be used to carry the target chip, and the upper substrate can be used to carry the top chip. Through the support of the upper and lower substrates, the stacking of multilayer chip packaging structures in the vertical direction can be realized, thereby realiz...

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Problems solved by technology

[0004] However, encapsulating chips with two substrates makes the entire package structure (including: upper substrate, MC, target chip and lower substrate) thicker (for example, about 490 microns (μm)), which cannot meet the needs of semiconductor packaging in current technologies. The demand for smaller and thinner is also not conducive to the heat dissipation of the chip

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