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Single event upset-resistant satellite-borne data processing system and method

An on-board data and anti-single particle technology, applied in aerospace electronics integration and aviation fields, can solve the problems of difficult software upgrade and maintenance, small memory capacity, and inability to maintain on-orbit, so as to improve the ability to resist single-event overturn, storage The effect of large capacity and reduced requirements for hardware circuit design

Active Publication Date: 2017-04-05
NAT SPACE SCI CENT CAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The purpose of the present invention is to overcome the defects of high cost, difficult software upgrade and maintenance, small memory capacity, and inability to maintain on-orbit in the exi

Method used

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  • Single event upset-resistant satellite-borne data processing system and method
  • Single event upset-resistant satellite-borne data processing system and method
  • Single event upset-resistant satellite-borne data processing system and method

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Embodiment Construction

[0065] The present invention is described in further detail now in conjunction with accompanying drawing.

[0066] Such as figure 2 Shown, a kind of on-board data processing system of anti-single-event upset, said system comprises: CPU, FLASHFPGA, SDRAM, first NOR FLASH, SRAM FPGA, NAND FLASH and second NOR FLASH; Wherein, described CPU The data, address and control buses are connected to the FLASH FPGA and the SDRAM, and the said FLASH FPGA is connected to the first NOR FLASH, the SRAM FPGA, the NAND FLASH and the second NOR FLASH.

[0067] The EMI module of the CPU has an ECC codec function, and the CPUs commonly used in aerospace are AT697 and Loongson LS1E. The interface between the CPU and the outside includes two asynchronous serial ports TXD, RXD and EJTAG.

[0068] The FLASH FPGA is used for CPU software guidance, SRAM FPGA configuration and refresh, and NAND FLASH control. In order to eliminate the single event flip effect of space radiation, all logic of the FLASH...

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Abstract

The invention discloses a single event upset-resistant satellite-borne data processing system. The system comprises a CPU, a FLASH FPGA, an SDRAM, a first NOR FLASH, an SRAM FPGA and a NAND FLASH, wherein data, an address and a control bus of the CPU are connected with the FLASH FPGA and the SDRAM; the FLASH FPGA is connected with the first NOR FLASH, the SRAM FPGA and the NAND FLASH; an EMI module of the CPU has an ECC encoding/decoding function; the FLASH FPGA is used for CPU software guidance, SRAM FPGA configuration and refreshing and NAND FLASH control; all logic of the FLASH FPGA is subjected to triple modular redundancy design; the SDRAM is used for CPU software running, and stored data is subjected to ECC encoding so as to realize "single-error-correcting and double-error-detecting" fault tolerance; and the first NOR FLASH is used for storing a startup program of the CPU, an application of the CPU and a configuration program of the SRAM FPGA. The system has the advantages of high reliability, in-orbit updating, low cost and large storage capacity, and can realize single event upset resistance.

Description

technical field [0001] The invention relates to the technical field of integrated aviation and spaceflight electronics, in particular to an on-board data processing system and method capable of resisting single-event reversal. Background technique [0002] The development of aerospace electronic integration technology is closely related to the development of computer technology, digital data communication technology, control technology and electronic technology, and they promote each other. The charged particles in the space radiation environment will cause the abnormal operation of the spaceborne electronic equipment and the failure of the device, which will seriously affect the reliability and life of the spacecraft. Therefore, there is a big gap between the spaceborne data system and the spaceborne data processing method and the ground data processing, mainly because of the resistance to the single event effect, among which the single event upset is the most frequent occu...

Claims

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Application Information

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IPC IPC(8): G06F9/445G06F11/10
Inventor 安军社周莉薛长斌谭羽茵郝澄
Owner NAT SPACE SCI CENT CAS
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