Operation device and method of accelerating chip which accelerates depth neural network algorithm

Abstract

The invention provides an operation device and method of an accelerating chip which accelerates a depth neural network algorithm. The device comprises a vector addition processor module which carries out addition or subtraction of vectors and / or the vector operation of a pooling layer algorithm in the depth neural network algorithm, a vector function value operator module which carries out the vector operation of the nonlinear evaluation in the depth neural network algorithm, and a vector multiply adder module which carries out the multiply addition operation of the vectors. The three modules execute a programmable instruction and interact with each other to calculate a neural network output result and a synaptic weight change amount which represents the neuron action intensity between neural layers. The three modules are provided with middle value storage areas and carry out reading and writing operations on a master memory. Thus, the reading and writing frequencies of the middle value of the master memory can be reduced, the energy consumption of the accelerator chip can be reduced, and the data loss and replacement problems in a data processing process can be avoided.

Description

technical field [0001] The invention belongs to the field of neural network algorithm and the field of computer hardware. More specifically, the present invention relates to a computing device and method of an acceleration chip for accelerating deep neural network algorithms. Background technique [0002] Artificial neural network algorithm is a research hotspot in the field of artificial intelligence since the 1980s. It abstracts the human brain neuron network from the perspective of information processing, establishes a simple model, and forms different networks according to different connection methods. It has a self-learning function, which can gradually learn to recognize and predict through training; associative storage function, with high algorithm robustness; high parallelism, with the ability to find optimal solutions at high speed, and can quickly find optimal solutions for complex problems of big data; It has strong plasticity and can fully approach any complex ...

AI Technical Summary

Problems solved by technology

A major problem that will be faced is that a large number of intermediate values ​​are generated and need to be stored, so that the required main memory space increases

At the same time, this method increases the number of times the intermediate value is stored in the main memory or read from the main memory, and the power consumption of the chip increases, which does not conform to the low-power accelerator chip design concept described above.

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