Real-time flat-field correction method of area array camera based on FPGA

Abstract

This invention combines the parallel computing characteristics of FPGA and takes into account the limited resources in FPGA, and proposes an optimized real-time flat field correction method for area array cameras that can be implemented based on FPGA. It uses a block-based computing method to perform block operations on the sensor array. , combined with the interpolation algorithm on the basis of blocks, to reduce resource consumption and perform operations on each point at the same time. The invention provides the possibility to implement a real-time FFC correction algorithm for high-resolution and high-frame-rate lower-array cameras, and provides higher output image quality for high-resolution and high-frame-rate applications. By using optimization algorithms, PRNU and vignetting effects were successfully corrected in real time while meeting the requirements of high resolution and high frame rate.

Description

technical field [0001] The invention relates to the technical field of image algorithms, in particular to an FPGA-based real-time flat-field correction method for an area array camera. Background technique [0002] In photoelectric imaging systems, especially in area array camera imaging systems, the image signal cannot fully reflect the actual target. The reasons mainly include two aspects: (1) The response inconsistency caused by the CCD or CMOS sensor manufacturing process (also known as PRNU ); (2) The vignetting effect caused by optical diffraction phenomena and various deviations of the optical system. In order to ensure the quality of the image output, it is generally necessary to correct the acquired original image with a flat-field correction (FFC) algorithm to make it meet the application requirements. Since PRNU and vignetting effects are often non-linear, in the FFC algorithm, correction is mainly performed by multiplication. The FFC algorithm can be summarized...

AI Technical Summary

Problems solved by technology

But for the high-resolution FFC algorithm, FPGA also has its own shortcomings, that is, the internal resources are limited, and it may not be able to cope with the storage resource requirements of high-resolution images.

For example, for KAI-47051, the number of pixels is 47.8MB, that is, based on the minimum 8-bit per pixel, 47.8MB of storage space is required to save the AI ​​array corresponding to an image; It is also difficult for FPGAs to meet this requirement

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