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Method for reducing data remanence in nonvolatile memory

A data residual and non-volatile technology, applied in the field of information security, can solve problems such as simulation verification, achieve a wide range of applications, and reduce data residual effects

Active Publication Date: 2016-09-21
TIANJIN UNIV
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  • Claims
  • Application Information

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However, there are no articles or patents proposing how to simulate and verify these influencing factors

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  • Method for reducing data remanence in nonvolatile memory
  • Method for reducing data remanence in nonvolatile memory

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Embodiment Construction

[0034] The basic structure for storing data in non-volatile memory is the floating gate cell, such as figure 1 shown. The charge stored in the non-volatile memory cell structure is the floating gate. The floating gate sits between the control gate and the substrate and is surrounded by an insulating layer whose wide bandgap forms a barrier that prevents electrons from flowing into or out of the floating gate. The logic "0" and logic "1" states of a non-volatile memory cell can be distinguished based on the amount of negative charge on the floating gate, which is determined by the programming operation. Program operation is divided into write operation and erase operation. The write operation utilizes the hot electron injection effect of the channel, so that electrons flow into the floating gate, the negative charge on the floating gate increases, and the threshold voltage V of the transistor th Rising, higher than the gate-source voltage V applied during the read operation ...

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Abstract

The invention discloses a method for reducing data remanence in a nonvolatile memory. The method comprises the steps of: carrying out structural modeling and electrical characteristic modeling on a non-volatile memory cell by Silvaco TCAD; determining model parameters corresponding to the factors affecting the data remanence in the non-volatile memory in a structural model and an electrical characteristic model; by use of the control variate method, determining the influence of any influence factor on the data remanence in the non-volatile memory according to a 0.18micron standard CMOS technology and calculating the quantity of floating gate electrons corresponding to floating gate charges; and reducing the quantity of the floating gate electrons by reducing the thickness of a tunnel oxide layer or increasing source voltage in an erasure operation or prolonging the erasure operation time, and selecting a model parameter value of the minimum quantity of the floating gate electrons to apply to the technical manufacturing process and the working process of a device, so that an attacker guesses stored data more difficultly according to the quantity of the floating gate electrons, namely the probability of restoring the data is effectively reduced.

Description

technical field [0001] The invention relates to safe storage of a non-volatile memory, in particular to the problem of data residue related to a floating gate structure in the non-volatile memory, and belongs to the technical field of information security. Background technique [0002] With the rapid development of information storage technology, solid-state storage technology has been widely used. Solid-state memory can be divided into volatile memory and non-volatile memory. Compared with volatile memory, which loses data when power is turned off, non-volatile memory can still retain the data in it when the power supply is temporarily interrupted or in a power-off state for a long time [1] . At present, solid-state storage technology with non-volatile memory as the core is widely used in computers, automobiles, mobile devices, communications and medical treatment. [0003] However, no memory of any kind is absolutely safe. The application of non-volatile memory is base...

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Application Information

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IPC IPC(8): H01L21/04G11C16/02G11C16/26H01L27/115
CPCG11C16/0408G11C16/26H01L21/04H10B69/00
Inventor 赵毅强王佳辛睿山何家骥李雪民
Owner TIANJIN UNIV
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