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VLSI (Very Large Scale Integration) formal verification platform and method

A large-scale integrated circuit and formal verification technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of large time overhead, multiple chip levels, and large differences in modules, so as to reduce the reading time the effect of consumption

Inactive Publication Date: 2016-08-24
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The technical problem to be solved by the present invention is: in consideration of the rapid development of the scale and complexity of today's integrated circuits, leading to various challenges in the comprehensive work, the present invention proposes a very large scale integrated circuit (VLSI) formal verification platform and method , considering that the scale of VLSI is too large, there are problems of high resource requirements and large time overhead in top-down synthesis. At the same time, there are many chip levels and large differences in modules. The bottom-up strategy is adopted to realize the verification platform in a modular manner. components

Method used

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  • VLSI (Very Large Scale Integration) formal verification platform and method

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Embodiment 1

[0027] Such as figure 1 As shown, a VLSI formalized verification platform for VLSI, the verification platform includes components: variable setting script, Lib read-in script, DUT read-in script, Env setting script, Report setting script, and the verification platform also includes The match / unmatch point extraction script that processes the output results of the verification platform, once the detection verification fails, there is an unmatch point, which can automate the iterative work, among which:

[0028] Variable setting script, which uniformly sets macro variables such as Lib / DUT read-in path, result output path, and top-level name to be tested. It is responsible for setting variables such as the top-level name, source path, report path, and library path of each DUT. It has a full platform Versatility;

[0029] Lib read-in scripts, manage the reading of standard cell libraries and various IPs (storage IP, PAD IP and other IP libraries), manage each module Lib separatel...

Embodiment 2

[0038] On the basis of Embodiment 1, the Env environment setting script described in this embodiment can be shared by all platforms.

Embodiment 3

[0040] On the basis of Embodiment 1 or 2, the match / unmatch point extraction script described in this embodiment is created using perl. There may be hundreds, thousands, or even more unmatch points in the verification, and the platform output format cannot be directly read into the platform environment. Therefore, using the powerful text processing capability of perl, a match / unmatch point extraction script is created. Once There is an unmatch point if the detection verification does not pass, which can automate the iterative work.

[0041] Perl, a feature-rich computer programming language that runs on more than 100 computer platforms and is applicable to a wide range of applications, from mainframes to portable devices, from rapid prototyping to massively scalable development; generally referred to as "Practical Report Extraction Language" "(Practical Extraction and Report Language), you may also see "perl", all letters are lowercase. Generally, "Perl", with a capital P, re...

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Abstract

The invention discloses a VLSI (Very Large Scale Integration) formal verification platform and method. The verification platform comprises components including a variable setting script, a Lib reading script, a DUT reading script, an Env setting script and a Report setting script. The verification platform further comprises a match / unmatch point extraction subscript for processing an output result of the verification platform. The VLSI formal verification platform and method use perl to realize the processing of the result, realize the automatic iterative verification of unmatch points, respectively manage source codes Lib of all modules to be verified and greatly reduce the consumption of reading time.

Description

technical field [0001] The invention relates to the technical field of chip formal verification, in particular to a VLSI formal verification platform and method. Background technique [0002] Today's VLSI has high complexity, large scale, and multiple layers. The overall verification of the whole chip (top-down strategy) has problems such as high resource requirements, large time overhead, and high iteration costs. Each layer and module do not match (unmatch) Situations vary, making debugging more difficult. [0003] The integration of digital integrated circuits is getting higher and higher, and the logic complexity and algorithms are becoming more and more complex. On the basis of ensuring timing, taking into account area and power consumption, the comprehensive work is facing great challenges. When the netlist flows into the back-end stage Before, it is necessary to ensure the functional equivalence of the synthesized netlist and the source code design. Formal verificat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/00
Inventor 张永照童元满李仁刚
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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