Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Schottky junction tunneling field effect transistor

A technology of tunneling field effect and Schottky junction, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., to achieve the effects of suppressing short channel effects, reducing electric field strength, and increasing width

Active Publication Date: 2016-08-17
HANGZHOU DIANZI UNIV
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method requires more advanced process technology, so it brings great challenges to the manufacturing process.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Schottky junction tunneling field effect transistor
  • Schottky junction tunneling field effect transistor
  • Schottky junction tunneling field effect transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be described in detail below in conjunction with the accompanying drawings.

[0016] Such as figure 1 A Schottky junction tunneling field effect transistor is shown, comprising a first gate 1, a source region 2, a drain region 3, a channel region 4, a heavily doped pocket region 5, a first gate dielectric layer 6, a second A gate 8 and a second gate dielectric layer 7; wherein the upper and lower sides of the channel region 4 are respectively provided with a first gate dielectric layer 6 and a second gate dielectric layer 7; above the first gate dielectric layer 6 is provided with a first gate 1. A second gate 8 is provided under the second gate dielectric layer 7; the first gate 1, the first gate dielectric layer 6, the second gate 8 and the second gate dielectric layer 7 maintain vertical symmetry; the source region 2 and The drain region 3 is ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a schottky junction tunneling field effect transistor, which comprises a first gate, a source region, a drain region, a channel region, a heavily-doped pocket region, a first gate dielectric layer, a second gate and a second gate dielectric layer. Heavily-doped silicon or other semiconductor material is replaced with metal or metal silicide in the drain region to form a schottky contact on the contact surface of the drain region and a channel. Due to the presence of a schottky barrier, band bending of the channel region of a device becomes slow, and the width of a tunneling barrier of the device is increased. Due to the presence of the schottky barrier, electric field distribution in the channel region and the drain region of the device is effectively adjusted, and the electric field intensity near a schottky junction is reduced. Therefore, the short-channel effect can be effectively inhibited by the schottky junction tunneling transistor; and the schottky junction tunneling transistor still has a relatively good switching characteristic when the feature size is reduced to sub-10 nanometers.

Description

technical field [0001] The invention relates to a device for semiconductor integrated circuits, mainly a schottky junction tunneling field effect transistor. Background technique [0002] In order for TFET devices to be used as ideal switching devices in ultra-low power consumption circuits, the reduction of the feature size of TFET devices must meet the International Technology Roadmap for Semiconductor (ITRS). However, with the continuous shrinking of the device feature size, the short-channel effect seriously affects the switching characteristics of the device. Since the region where band-band tunneling occurs in TFET devices is very small, traditional p-i-n structure TFET devices have good scalability even without the use of advanced technology. However, when the feature size of TFET is reduced to the range of sub-30 nanometers, the performance of the device will be seriously affected, which is mainly due to the formation of a certain intensity of electric field in the ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/10H01L29/423H01L29/739
CPCH01L29/1025H01L29/42312H01L29/7391
Inventor 王颖曹菲王艳福于成浩
Owner HANGZHOU DIANZI UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products