Cell recess oxide etching method of improving deep-submicron flash memory device coupling rate

Abstract

The present invention provides a cell recess oxide etching method of improving a deep-submicron flash memory device coupling rate. The method is characterized by combining a first dry etching step, a wet etching step and a second dry etching step; the dry etching effectively overcomes the characteristic that the density of the filling oxides is uneven, and the oxides in a density loose area at an opening in a cell recess are removed by the first dry etching step, so that the subsequently etched oxide interfaces are same in height and even and consistent in density; then, the oxide side walls at the side walls of the polycrystalline floating gates caused by the first dry etching are removed by the wet etching, so that the side walls are totally not covered by the oxides; and then, the cell recess oxide bottoms of consistent height and the oxide side walls at the bottoms of the side walls of the polycrystalline floating gates of uniform morphology and protecting the tunneling oxide layers are realized by the second dry etching, and then the ONO deposition is carried out to form the consistent ONO capacitors formed by the contact of the ONO and the polycrystalline floating gates, thereby achieving the purposes of improving the coupling rate of a deep-submicron flash memory device and improving the product qualified rate and service life.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a trench oxide etching method for improving the coupling rate of deep submicron flash memory devices. Background technique [0002] With the continuous development of integrated circuit manufacturing process, the feature size of devices is also continuously reduced. The technology of submicron and deep submicron flash memory devices is becoming more and more mature. As an important structure for storing data in flash memory devices, polycrystalline floating gate transistors have been improved by the market. requirements are quite urgent. [0003] figure 1 It is the basic structure of a polycrystalline floating gate transistor as a basic storage unit (cell). [0004] As shown in the figure, each polycrystalline floating gate transistor is a three-terminal device, which are source 1, drain 2 and gate 3 respectively. The effect of the electric field is us...

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Problems solved by technology

[0018] The technical problem to be solved by the present invention is to reduce the difference in height of the bottom of the oxide in the trench, unify the oxide sidewall of the polycrystalline floating gate, and uniform the contact area between ONO and the sidewall of the polycrystalline floating gate, so as to realize the improvement of deep submicron flash memory The coupling rate of the device is the ultimate goal of improving the product qualification rate and service life

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