Dynamic random access memory

Abstract

The invention provides a dynamic random access memory, comprising a substrate, buried word lines and active areas which are positioned in the substrate, bit lines and capacitors. The long edge directions of the active areas and the extension directions of the bit lines form acute angles theta, and the bit lines are positioned on the substrate and cross the buried word lines. Each buried word line divides the active areas arranged on the same column into two contact areas, and each bit line is electrically connected with the adjacent contact areas on two sides of each buried word line. The capacitors are arranged between the bit lines, and each capacitor is electrically connected with the adjacent contact areas on two sides of each buried word line. Thus, in each active area, one contact area is electrically connected with one capacitor, while the other contact area is electrically connected with one bit line.

Description

technical field [0001] The present invention relates to a dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM), and in particular to a dynamic random access memory capable of reducing the area of ​​components. Background technique [0002] In order to improve the integration level of DRAM, speed up the operation speed of components, and meet the needs of consumers for miniaturized electronic devices, a buried word line DRAM (buried wordline DRAM) has been developed in recent years to meet the above-mentioned requirements. Various needs. [0003] For example, for reducing the area of ​​the device, there is currently an embedded word line DRAM designed by developing word lines, active regions and bit lines with different extending directions. [0004] However, the above-mentioned DRAM still has room for reduction, and the circuits with increasingly smaller pitches will also cause the problem of interference between components when operating the com...

AI Technical Summary

Problems solved by technology

[0004] However, the above-mentioned DRAM still has room for reduction, and the lines with increasingly smaller pitches will also cause the problem of interference between components when operating components.

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