An integrated structure of an LDMOS and a JFET and a manufacturing method thereof

Abstract

The invention discloses an integrated structure of an LDMOS and a JFET and a manufacturing method thereof. The JFET uses a drift region and a drain region, which are also the drift region and the drain region of the LDMOS. A first polysilicon layer is connected in an end to end mode to form a closed first polysilicon encircling structure. A source region and a channel region of the LDMOS respectively circle around the outer side of the first polysilicon layer to form a source region encircling structure with an opening. A gate electrode region and a source region of the JFET form in a deep N-well outside an opening position, so that a gate electrode region of the JFET and the channel region of the LDMOS are separated. The invention also discloses a manufacturing method for the integrated structure of the LDMOS and the JFET. According to the invention, high-voltage resistance of the JFET can be realized; meanwhile, the reliability of the LDMOS device can be raised; and relatively low cost is realized.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a junction field effect transistor (JFET) device. The invention also relates to a manufacturing method of the JFET device. Background technique [0002] In the current high-voltage BCD process, the commonly used method of high-voltage LDMOS with high-voltage JFET is to use the structure of high-voltage LDMOS to provide withstand voltage, and then draw the source region (Source) of JFET at the other end of the high-voltage N well (HVNwell) to form a high-voltage JFET device. [0003] By using the drift region of the isolated high-voltage LDMOS as the drain region or the source region (Drain / Source) of the JFET, and using the body region (body) of the LDMOS, that is, the P well (Pwell) of the channel region, as the JFET gate region (Gate), Realize the JFET parasitic in the LDMOS, and realize the high withstand voltage performance of the JFET through th...

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Problems solved by technology

[0024] The JFET and LDMOS of the above-mentioned existing structure share the drift region and the drain region, which can realize the high durability of the JFET, but the disadvantage is that the gate region of the JFET and the channel region of the LDMOS share the P well 105a, and at a higher operating voltage (> 300V), the flow of electrons in the JFET channel will cause holes to be injected into the P-well 105a to generate a hole current. The higher the voltage, the greater the current, which will eventually cause high-voltage LDMOS reliability problems

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