Implementation method of AntNet routing algorithm in two-dimensional mesh topology network-on-chip

Abstract

The invention provides an implementation method of AntNet routing algorithm in a two-dimensional mesh topology network-on-chip. In combination with three characteristics that the network-on-chip has a small storage space compared with a computer network, the queuing delay influence is large and routers are tightly coupled, the implementation method improves the AntNet routing algorithm from three aspects of an ant package queue, an ant package generation way and an enhancing factor r, so that the AntNet routing algorithm is applicable to be implemented in the network-on-chip. In an AntNet router, an input port is divided into two queues, namely a data package and an ant package, wherein the priority of the ant package queue is higher than the data package queue; a forward ant package is only transmitted to routers in the two-dimensional mesh topology which are not located at the same row or same line of the router; and based on a learning automata theory, the calculation of the enhancing factor r is simplified. The AntNet routing algorithm has a good effect in improving the performance of the network-on-chip.

Description

technical field [0001] The invention relates to an implementation method of a two-dimensional grid topology on-chip network AntNet routing algorithm applied in system-level design of embedded processors, and belongs to the field of system-level design of embedded processors. Background technique [0002] At present, a single chip generally integrates dozens to hundreds of processing cores at most. The interconnection structure connecting these IP cores is mainly an on-chip bus, which completes the communication between different master and slave components through arbitration and decoding. Multiplexed with media. In the near future, with the continuous development of integrated circuit manufacturing technology, the scale of integrated circuits will exceed billions of transistors. In order to meet market demand, a single chip will require the integration of hundreds or thousands of processing cores. As a result, interconnect structures based on on-chip buses face increasingl...

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Problems solved by technology

[0010] Technical problem: the purpose of the present invention is to solve the AntNet routing algorithm originally applied in the computer network because of the small storage space, the large impact of queuing delay, and the tight coupling between routers compared with the computer network. Problems in implementation in a network-on-chip, and a low-overhead practical implementation of the AntNet routing algorithm in a two-dimensional grid topology network-on-chip is proposed

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