Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for monitoring fuse burning yield rate in chip test

A technology of chip testing and fuse burning, which is applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as test product loss, and achieve the effect of avoiding irreversible loss

Active Publication Date: 2016-04-06
WUXI ZHONGWEI TENGXIN ELECTRONICS
View PDF5 Cites 19 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the large number of machines in the production line, it is impossible for the operator to pay attention to the situation of a certain test machine in real time, so it may cause irreversible losses to the test products in this process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for monitoring fuse burning yield rate in chip test
  • Method for monitoring fuse burning yield rate in chip test
  • Method for monitoring fuse burning yield rate in chip test

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0025] In this embodiment, the method for monitoring the achievement rate of burning the fuse in the chip test includes the following steps:

[0026] Step S1, establish a fuse truth table, as shown in the following table;

[0027]

[0028] In this example, the number of fuses is four sections. After a certain section of fuse is blown, the change in the reference voltage of the chip has been specified in advance during the fuse design process. In this example, the changes in the reference voltage after each section of fuse is blown are respectively : -12.5mV(T3-GND), -25mV(T2-GND), -50mV(T1-GND), +100mV(T0-GND); T0-GND, T1-GND, T2-GND, T3-GND represent Four section fuse;

[0029] The fuse truth table has a minimum reference value of 500mv and a maximum reference value of 700mv; the fuse truth table also has a reference voltage standard value of 600mv; If t...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for monitoring the fuse burning yield rate in chip test, comprising the following steps: S1, a fuse truth table is established, wherein the fuse truth table contains the corresponding relation between the reference voltage measured value ranges of chips and fuses needing to be burnt out; S2, a chip is tested, and the reference voltage measured value of the chip is monitored; S3, the reference voltage measured value falls into a specific reference voltage measured value range, the chip is qualified if the reference voltage measured value falls into a reference voltage target range to which the reference voltage standard value belongs, and the chip fuses corresponding to the specific reference voltage measured value range are burnt out according to the corresponding relation between the reference voltage measured value ranges and the fuses needing to be burnt out in the fuse truth table if the reference voltage measured value is beyond the reference voltage target range; and S4, the fuses are burnt again if the fuses are not burnt out. By using the method of the invention, the fuse burning adjustment process in chip test can be monitored in real time.

Description

technical field [0001] The present invention monitors the achievement rate of fuse burning in the integrated circuit test, and performs real-time processing to improve the quality of the fuse burning. a method of Background technique [0002] The development of integrated circuits has put forward higher requirements for the accuracy and programmability of circuits. As the requirements for high-performance indicators of integrated circuits are getting higher and higher, integrated circuits are facing increasingly high-precision requirements. Trimming technology is a necessary means to realize high-precision integrated circuits. Fuse trimming plays an increasingly important role in traditional analog circuits and digital circuits with high precision requirements. In integrated circuits such as AC-DC, DC-DC, and LDO (low dropout linear regulator) It is widely used in (IC). Burning the fuse is not just as simple as adjusting the output voltage. It depends on the design. Its ma...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/66
CPCH01L22/14H01L22/20
Inventor 韩新峰
Owner WUXI ZHONGWEI TENGXIN ELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products