Digital circuit design method and related system

Abstract

The disclosure provides a digital circuit design method and a related system. The digital circuit design method includes: before physical design: performing logic synthesis according to a register transfer level design and a plurality of restriction conditions to at least generate a circuit program file, a standard delay format file, and a first restriction condition file ; Extract information of at least one specific node in the circuit from the first constraint file to generate a second constraint file; generate an updated standard delay at least according to the standard delay format file and the second constraint file format file, wherein the delay amount of the specific node in the updated standard delay format file is smaller than the delay amount of the specific node in the standard delay format file; and using the circuit program file and the updated standard delay format file to perform a Simulation after pre-circuit layout.

Description

technical field [0001] The invention relates to the technical field of circuit design, in particular to a digital circuit design method and a related system. Background technique [0002] The traditional digital circuit design is mainly divided into the front part and the back part. The front part mainly includes the Register Transfer Level (RTL) design, functional simulation, and logic synthesis. The part includes physical design, automatic circuit layout, and post layout simulation, etc. [0003] Generally speaking, it is not necessary to do functional simulation with timing delay information after logic synthesis and before the physical design is completed, and it is also difficult to do such simulation. For example, in the setting of logic synthesis, the circuit A node with a high load number (high fan-out net) in the logic synthesis will be marked with a huge delay time in the timing information (timing information), so that the circuit program file ( netlist) cannot ...

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Problems solved by technology

[0003] Generally speaking, it is not necessary to do functional simulation with timing delay information after logic synthesis and before the physical design is completed, and it is also difficult to do such simulation. For example, in the setting of logic synthesis, the circuit A node with a high load number (high fan-out net) in the logic synthesis will be marked with a huge delay time in the timing information (timing information), so that the circuit program file ( netlist) cannot be simulated with this timing information

[0004] The above-mentioned nodes with high load numbers will undergo additional processing in the subsequent physical design so that the delay time will not be too long. However, if the post-circuit layout simulation is to be performed after the physical design is completed, because this time point It is usually close to the time of tape out. Therefore, if the problem is discovered after the circuit layout is simulated, it will often affect the product schedule.

[0005] For digital design, if the constraints set during logic synthesis are correct and sufficient, and the correct static timing analysis (static timing analysis) is performed accordingly to pass the verification, generally speaking, after the circuit layout is simulated and Errors are less likely to occur. However, sometimes due to errors occurring when engineers enter constraints, errors are not found during static timing analysis, but are only discovered after simulation after circuit layout, or in some designs. errors may also escape static timing analysis, only to be discovered after simulation after circuit layout

However, as mentioned in the previous paragraph, waiting until after the physical design is complete to discover such errors is usually too late

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