Semiconductor device and manufacturing method therefor

Abstract

The invention discloses a semiconductor device, and the device comprises a plurality of fins which extend in a first direction, a grid electrode which extends in a second direction and is across all the fins, source and drain regions which are located on fins at two sides of the grid electrode, and a grid electrode side wall. Each fin consists of a buffering layer and a trench layer made of high-migration-rate materials, and the buffering layers enclose the side and bottom surfaces of the trench layers. According to the invention, the device can locally form a high carrier mobility trench in a self-alignment manner on a needed fin structure through removing false grid stacking and increasing an etching depth and a lateral width, thereby effectively improving the carrier mobility of a fin trench region, and effectively improving the performance and reliability of the device.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional multi-gate FinFET with high carrier mobility and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects. [0003] For example, compared with the traditional single-gate body Si or SOIMOSFET, the double-gate SOI MOSFET can suppress the short-channel effect (SCE) and drain-induced barrier lowering (DIBL) effects, and has lower junction capacitance. The channel is lightly doped, and the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double...

AI Technical Summary

Problems solved by technology

Compared with the aforementioned method, although this method reduces the distribution of SiGe and Ge materials on the entire wafer, that is, the growth of some local spaces to a certain extent, as long as the fin structure on the top of the STI is exposed, the Ge epitaxial layer will grow. For other device regions on the wafer that need to further improve the electron mobility, it is difficult to adopt a CMOS compatible process to manufacture in one step, that is, an additional mask photolithography / etching process is often required, which increases the complexity of the device and easily causes device lines. Distortion, and even device failure

In addition, since the bottom of the fin structure is monocrystalline silicon (bulk Si or SOI top monocrystalline silicon) during epitaxial growth, and the STI on both sides of the epitaxial layer is amorphous oxide, it is easy to produce localized silicon during the epitaxial process. Lattice defects

Images