Safe chip power-down testing equipment

Abstract

The invention discloses safe chip power-down testing equipment which comprises the components of a master control module, a switching module and a chip insertion slot. The master control module communicates with an upper computer through a USB interface and performs functions of receiving a power-down instruction of the upper computer and analyzing the power-down instruction for obtaining a power-down control signal. The master control module transmits the power-down control signal to a to-be-tested chip in the chip insertion slot through the switching module, thereby controlling the to-be-tested chip for performing power-down operation. The safe chip power-down testing equipment controls a bidirectional converting chip through a single-chip microcomputer for performing power-on operation and power-down operation. Short time delay and accurate time are realized. The safe chip power-down testing equipment supports testing of a 7816-interface chip and testing of an SPI-interface chip, thereby realizing wide application range. Power-down operation is controlled through an APDU command. The safe chip power-down testing equipment has advantages of multiple power-down starting point setting modes, high use flexibility and more comprehensive testing.

Description

technical field [0001] The invention relates to the technical field of power-down testing of smart chips, in particular to a power-down testing device for a security chip. Background technique [0002] The power-down test is an important test for the security chip of the smart meter. It is mainly to assess whether the internal data, especially the data in the EEPROM, will be rewritten when the security chip suddenly loses power during the communication process. The main workflow of the power-off test is: power on the security chip correctly, send a test APDU command to the security chip, after sending the test APDU, suddenly power off at an uncertain time, and restart Power on the chip, send a verification APDU command to verify the chip, and analyze whether the internal data of the chip has been rewritten. [0003] In the existing technology, the power-down test is mainly carried out for the 7816 interface chip, and it supports two kinds of power-down start point selection...

AI Technical Summary

Problems solved by technology

[0008] In order to solve the problem in the prior art that the SPI interface security chip cannot be effectively tested for power-down, the present invention proposes a security chip power-down test device

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