A dll output circuit and a method for ensuring that dram power-saving mode exits normally

Abstract

The invention relates to a DLL output circuit and a method for guaranteeing that a DRAM power saving mode normally exits. The DLL output circuit comprises a receiver, a DLL delay chain, an output phase discriminator, a DDL logic controller, a delay control chain and a reactive circuit, and also includes a counter and an arithmetic unit, wherein an input end of the counter receives a trigger enable signal and configuration parameters; an output end of the counter is connected with the arithmetic unit; the arithmetic unit links the delay chain controller; and the counter takes the configuration parameters as the radix, and can count under the trigger enable signal effect. The DLL output circuit and the method for guaranteeing that a DRAM power saving mode normally exits can solve the technical problem that an existing DLL output circuit cannot compensate transient voltage disturbance when the abrupt change of current occurs, and the internal power supply system in the DRAM is not stable. The DLL output circuit and the method for guaranteeing that a DRAM power saving mode normally exits can automatic compensate to realize transient compensation of noise when the DRAM power saving mode exits.

Description

technical field [0001] The invention relates to a method for solving the abnormal exit of DRAM power saving mode. Background technique [0002] In order to meet the power-saving requirements of the JEDEC standard, existing DRAM products often turn on all clocks and corresponding modules inside the chip only when responding to read commands. This kind of operation can bring great power saving effect, so the DRAM industry has continued this kind of control. However, as the speed of DRAM becomes faster and faster, sudden read commands often cause huge transients to the internal and external power supply systems of the chip. Consumption makes the internal power supply system of DRAM unstable, resulting in the effective width of the data information generated by DRAM being too short, and even logic errors caused by insufficient internal logic timing. Under normal circumstances, the DLL output circuit will run through hundreds of cycles. Generally, for DDR1, the DLL delay chain l...

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Problems solved by technology

[0004] In order to solve the technical problem that the existing DLL output circuit cannot compensate for the transient voltage disturbance in the face of a sudden change in the current situation, and the internal power supply system of the DRAM is unstable, this paper provides a DLL output circuit and ensures that the DRAM power-saving mode exits normal way

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