A forward error correction code processor

Abstract

The invention discloses a forward error correcting code processor. The forward error correcting code processor comprises a reading linearity address generator, a writing linearity address generator, a reading transformation address generator, a writing transformation address generator, memory banks, operation performing units, a transposition network and a reverse transposition network, wherein the reading linearity address generator is connected with the reading transformation address generator, the reading transformation address generator is connected with the memory banks, the memory bank is connected with the operation performing unit through the transposition network, the operation performing unit is connected with the memory bank through the reverse transposition network, the memory banks are connected with the writing transformation address generator, the writing transformation address generator is connected with the reading linearity address generator, the memory banks and the operation performing units are multiple, the multiple memory banks realize mutual data exchange through the transposition network, and calculation results of the operation performing units are written back to the memory banks through the reverse transposition network. Through the forward error correcting code processor, decoding efficiency and flexibility are improved.

Description

technical field [0001] The invention relates to the communication field, in particular to a forward error correction code processor. Background technique [0002] At present, there are many standards in the field of mobile communication, and the update and iteration speed is fast. In addition to the mainstream mobile communication standards (such as GSM, EDGE / GPRS, HSPDA, UMTS, 3GPP LTE, 802.11n, 802.16e, etc.) that require forward error correction code (FEC) support, more military and other non-commercial standards FEC support is also required. The decoding algorithms in these standards are quite different, and the requirements and algorithms may not be fully known at the time of tape-out. Therefore, the degree of specialization and customization of such applications is high, and the cost of tape-out of individual chips is too high, and high-flexibility chip compatibility is usually required. At the same time, this type of application has certain requirements for decodin...

AI Technical Summary

Problems solved by technology

Its solution has more analysis on area cost savings, but little analysis on flexibility. Its programming ability and ability to be compatible with unknown protocols are not mentioned, and there is no corresponding configuration on the hardware.

[0009] In addition, there are also a large number of software radio solutions that use general-purpose GPUs, DSPs, or CPUs to implement Viterbi, Turbo, and LDPC decoding. Their general characteristics are low power consumption and limited decoding rate. Without an effective processing structure, it cannot be used in power-sensitive occasions such as mobile terminals

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