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Shift register unit, gate line driving device and driving method

A shift register and reset signal technology, applied in static memory, digital memory information, instruments, etc., can solve the problems of signal output delay, gate line output failure, heavy load, etc., to reduce signal delay, improve signal waveform, improve reliability effect

Active Publication Date: 2017-12-29
BOE TECH GRP CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because the size of the transistor that pulls down the output of the shift register unit is generally large, the use efficiency is low, which is not conducive to reducing the circuit size and power consumption; The triggering of the shift register unit of the stage is completed by the signal output by the output transistor of the shift register unit of the present stage. Therefore, the load of the output transistor of the shift register unit of the present stage is relatively large, resulting in a signal output delay; in addition, if the output Failure of the transistor will not only lead to poor signal output to the gate line corresponding to the current stage, but also cause output failure of the gate line corresponding to the previous stage and the next stage

Method used

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  • Shift register unit, gate line driving device and driving method
  • Shift register unit, gate line driving device and driving method
  • Shift register unit, gate line driving device and driving method

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Embodiment Construction

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts also belong to the protection scope of the present invention.

[0031] figure 1 A circuit structure of a known shift register unit is illustrated. like figure 1 As shown, the shift register unit includes: an input transistor M1, whose gate and drain are connected together and connected to the input terminal of the shift register unit, and whose source is connected to the pull-up node PU; an output transistor M3, whose The gate is connected to the pull-up node PU, the drain is connected to the first clock signal terminal CLK, and the source is connected to the ou...

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Abstract

A shift register unit, a gate line driving device including a multi-stage shift register unit, and a driving method for the shift register unit, wherein the shift register unit includes: an input module connected to an input terminal and a pull-up Between the nodes, the pull-up node is charged; the output module is connected between the pull-up node, the first clock signal terminal and the output terminal, and is configured to output the first clock signal connected to the first clock signal terminal to the output terminal ;The pull-up node reset module is connected between the reset terminal, the pull-down node and the pull-up node, and is configured to reset the pull-up node; the output reset module is connected between the second clock signal terminal, the pull-down node and the output terminal , configured to reset the output. According to the shift register unit, the gate line driving device and the driving method for the shift register unit of the present disclosure, the size of the overall structure of the GOA can be reduced, the power consumption can be reduced, the delay of the signal can be reduced, the signal waveform can be improved, and the Overall reliability of the GOA circuit.

Description

technical field [0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate line driving device including the shift register unit, and a driving method for the shift register unit. Background technique [0002] In the field of display technology, a pixel array such as a liquid crystal display usually includes multiple rows of gate lines and multiple columns of data lines that are staggered. Wherein, the driving of the gate lines can be realized through an attached integrated driving circuit. In recent years, with the continuous improvement of the amorphous silicon thin film technology, the gate line driving circuit can also be integrated on the thin film transistor array substrate to form a GOA (Gate driver OnArray) to drive the gate line. [0003] Among them, the GOA composed of multiple shift register units can be used to provide switching signals for multiple rows of gate lines in the pixel array, thereby c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/36G11C19/28
CPCG09G3/3677G11C29/022G11C19/18G11C19/184G11C19/287G09G2310/0286G11C19/28G11C29/86G09G3/3685G09G2310/0283G11C7/1036G11C19/30
Inventor 王峥
Owner BOE TECH GRP CO LTD
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