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A General Matrix Optimization Method for Accelerating Erasure Code Encoding and Decoding Process

An optimization method and erasure code technology, applied in the field of erasure code, can solve problems such as too many times of data block operations, poor codec performance, lack of parallel capability, etc., and achieve the effect of shortening time and improving codec performance

Active Publication Date: 2018-05-22
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

However, the existing encoding and decoding algorithms lack parallelism when realizing the operation of matrix and data blocks, and at the same time, the number of operations on data blocks is too many, which makes the encoding and decoding performance poor.

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  • A General Matrix Optimization Method for Accelerating Erasure Code Encoding and Decoding Process
  • A General Matrix Optimization Method for Accelerating Erasure Code Encoding and Decoding Process
  • A General Matrix Optimization Method for Accelerating Erasure Code Encoding and Decoding Process

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Embodiment Construction

[0019] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0020] Some new definitions will be used in the embodiments of the present invention, and the nouns are explained as follows:

[0021] Stripe (stripe): it is the basic unit for applying erasure code to protect data in the present invention. A disk array is logically divided into multiple stripes, and each stripe spans multiple disks, occupying the same capacity in these disks. Data is protecte...

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Abstract

The invention discloses a universal matrix optimization method for accelerating erasure correcting code encoding and decoding processes. The method comprises the steps of: during encoding and decoding, decomposing a check matrix into a plurality of mutually independent sub-matrixes and a residual sub-matrix to enable encoding and decoding operation to be partially executed in parallel; and in addition, adjusting a matrix calculation sequence to reduce data block calculation frequency involved in the encoding and decoding processes so as to reduce the time cost for calculation. The method improves the performance of the erasure correcting code encoding and decoding processes, especially the performance of operation in a multi-core processor. The encoding and decoding processes realized by using the method can utilize potential parallel encoding capability, make full use of parallel processing capability of the multi-core processor and shorten the calculation time.

Description

technical field [0001] The invention belongs to the technical field of erasure codes, and more specifically relates to a general matrix optimization method for accelerating the encoding and decoding process of erasure codes. Background technique [0002] Erasure coding is a technology that generates redundant data blocks through encoding to achieve data protection. Erasure coding technology is widely used in disk arrays to improve reliability. For erasure codes that use Galois field operations for encoding and decoding, the encoding and decoding process usually involves matrix and data block operations. However, the existing encoding and decoding algorithms lack parallelism when realizing the operation of matrix and data blocks, and the number of operations on data blocks is too many, which makes the encoding and decoding performance poor. Contents of the invention [0003] In view of the above defects or improvement needs of the prior art, the present invention provides...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F11/10
Inventor 曹强万胜刚张文辉李诗逸黄建忠谢长生
Owner HUAZHONG UNIV OF SCI & TECH
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