Chip packaging structure and manufacture method thereof

Abstract

The invention provides a chip packaging structure and a manufacture method thereof. The chip packaging structure comprises a first pin, a first conductive post positioned on the first pin, and a second pin positioned on a second conductive post and electrically connected with the second conductive post and a first electric connecting body on a chip active surface, wherein an electrode bonding pad on the chip active surface is led out through a conductive path comprising the first electric connecting body, the second pin, the first conductive post and the first pin, and finally the electric connection between a chip and an external circuit is realized through the first pin. The mode for leading out the electrode can effectively reduce packaging resistance, does not need solder for welding, can avoid the phenomenon of pseudo soldering, improves the chip packaging reliability, and effectively reduces the chip packaging thickness.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] In the traditional chip front-mount package structure, the non-active surface of the chip is adhered to the chip carrier plate of the lead frame, and the electrodes on the active surface of the chip are electrically connected to the pins around the carrier plate through metal leads, so that the The electrodes on the active surface of the chip are drawn out to connect with external circuits. [0003] Although this traditional wire bonding packaging method has a relatively mature process and a large output, it will inevitably lead to a large packaging resistance because it needs to use slender metal leads to lead out the electrodes on the chip surface. In addition, the metal leads and False soldering is prone to occur between the pads of the chip, which is not conducive to ensuring ...

AI Technical Summary

Problems solved by technology

[0003] Although this traditional wire bonding packaging method has a relatively mature process and a large output, it will inevitably lead to a large packaging resistance because it needs to use slender metal leads to lead out the electrodes on the chip surface. In addition, the metal leads and False soldering is prone to occur between the pads of the chip, which is not conducive to ensuring the reliability of the chip package

In recent years, with the development of thinner electronic devices, the traditional wire bonding packaging method has become increasingly unable to meet people's requirements due to the thicker packaging.

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