Multi-core processor directory cache replacement method

Abstract

The invention discloses a multi-core processor directory cache replacement method, and belongs to the technical field of computer storage. The multi-core processor directory cache replacement method comprises the following concrete steps that a multi-core processor adopts a two-stage caching structure, each processor core is combined into an L1 Cache, and all processor cores share an L2 Cache; the data consistency is maintained between the L1 Caches through a directory cache, and the number of no-message replacement times generated by a certain buffer group of the L1 Cache corresponding to each processor core is determined according to interactive messages of the directory cache and the L1 Caches; no-message replacement counting vector group of each L1 Cache group is additionally added for the directory cache, and the number of no-message replacement times generated by each L1 Cache in the cache group is stored, so that cache blocks to be replaced are determined. The multi-core processor directory cache replacement method has the advantages that invalid terms in the directory cache are effectively recognized, limited replacement is carried out, the effective capacity of the directory cache is improved, and the integral performance of the multi-core processor is improved.

Description

technical field [0001] The invention discloses a directory cache replacement method, which belongs to the technical field of computer storage, and in particular relates to a multi-core processor directory cache replacement method and a directory cache replacement system. Background technique [0002] The multi-core processor structure has become the mainstream of processor design. The multi-core structure is widely used in desktop processors, server processors, and even mobile phone processors, and the number of cores is increasing significantly. With the increase of the number of cores, the multi-core processor system has scalability, and then it is necessary to maintain the cache data consistency of multiple processor cores, and the directory consistency can effectively maintain the cache data consistency. However, the cache coherence protocol used in commercial processors leads to a waste of directory cache space. In order to reduce the response time (Load-To-Use Time) of...

AI Technical Summary

Problems solved by technology

However, the cache coherence protocol used in commercial processors leads to a waste of directory cache space. In order to reduce the response time (Load-To-Use Time) of L1Cache, the directory cache (Directory Cache) is often not notified when performing a downgrade operation on clean data.

Usually, if the L1Cache is replaced, the replaced cache block is in the S state. When the data in the S state is downgraded to the I state, the L1Cache does not need to communicate with the Directory Cache. Although this reduces the time delay of the replacement operation, the downgrade operation Directory Cache is not notified, and Directory Cache still maintains data consistency for I-state data

This leads to a waste of Directory Cache capacity due to invalid items caused by no-message replacement operations, causing more serious capacity conflicts in Directory Cache, and impairing the overall performance of multi-core processors.

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