Structure of AND and NOR-logic devices and making method

Abstract

The invention discloses a structure of AND and NOR-logic devices. The AND-logic device is made on a P-trap or P-type substrate, the P-trap or P-type substrate is connected to the ground, the upper face is provided with two neighboring control gates, for respectively controlling two neighboring n-type conducting channels which are connected in series; two ends of each control gate are provided with a highly doped n-type source region and a drain region, used as the leading-out ends of two n-type conducting channels; a polycrystalline silicon grid electrode is located above each control gate, and two polycrystalline silicon grid electrodes are mutually electrically separated and leaded out independently. The structure of the NOR-logic device is similar to the structure of the AND-logic device, the difference is to be made in a n-trap or n-type substrate, and the source and drain regions are the highly doped p-type. The invention further discloses a making method for the structure of AND and NOR-logic devices. The structure of the AND and NOR-logic devices is capable of, through designing the novel AND and NOR-logic device structure, simplifying the device and circuit structure, reducing the circuit area and making cost, and simplifying the sequential control of the circuit.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to the structure of AND and OR logic devices and its manufacturing method. Background technique [0002] Traditional AND gate logic circuits are implemented using 6 MOS (metal oxide semiconductor) transistors, including 3 nMOS (n-well channel metal oxide semiconductor) and 3 pMOS (p-type channel metal oxide semiconductor), such as figure 1 shown. The working principle of the AND gate logic circuit is: when the two input terminals A and B are at the high level "1" at the same time, the output terminal Y is at the high level "1", otherwise the output terminal Y is at the low level "0". [0003] The traditional NOR gate logic circuit is implemented using 4 MOS transistors, including 2 nMOS and 2 pMOS, such as figure 2 shown. The working principle of the NOR gate logic circuit is: when the two input terminals A and B are at the high level "1" at the same time, the out...

AI Technical Summary

Problems solved by technology

[0004] The disadvantages of these two logic circuits are that the circuit structure is complex, the chip area is large, and the cost is high.

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