Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The method comprises steps: a substrate is provided, and an element and an interconnection structure above the element are formed on the substrate; a benzocyclobutene dielectric layer or a polyimide dielectric layer is formed on the substrate; a metal pad is formed on the dielectric layer to be connected with the interconnection structure; and two wafers comprising the dielectric layer and the metal pad are bonded. In order to solve the problems in the prior art, a new material is selected as the dielectric layer in the horizontal wafer Cu-Cu bonding technology, benzocyclobutene (BCB) or polyimide is selected as the dielectric layer, bonding between the upper wafer and the lower wafer is realized, BCB of the upper wafer and the lower wafer can be melted together during the bonding process, a bonding pair free of a void is formed, and the bonding quality is improved. The BCB can serve as a blocking layer, and the problem of metal diffuse (such as Cu diffuse) between the wafers can be solved completely.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a semiconductor device and a preparation method thereof. Background technique [0002] In the field of electronic consumption, multi-function devices are more and more popular among consumers. Compared with devices with simple functions, the production process of multi-function devices will be more complicated, such as the need to integrate multiple chips with different functions on the circuit board, so 3D integrated circuit (integrated circuit, IC) technology, 3D integrated circuit (integrated circuit, IC) is defined as a system-level integrated structure, stacking multiple chips in the vertical plane direction, thereby saving space, the edge of each chip Multiple pins can be drawn out as needed, and these pins can be used to interconnect the chips that need to be connected to each other through metal wires, but the above method still has many shortcomings, ...

AI Technical Summary

Problems solved by technology

[0008] In the prior art, Cu pads in Cu-Cu bonding (Wafer level Cu-Cu bonding) are prepared by Damascene process, using oxide as a medium, patterning the trench pattern, and then filling the trench and planarizing Form copper metal pad patterns (Cu metal pattern) in a manner that uses oxide as the dielectric layer 105 of the top metal layer (top metal), which may cause copper diffusion (suffer Cu diffuse) question

[0009] In addition, there are still major technical difficulties in the formation of Cu-Cu bonding (Wafer level Cu-Cu bonding) in the prior art, such as the alignment of metal pads during bonding (bonding alignment), bonding quality problems (Bonding quality issue), the wafer edge caused by stress during the wafer bonding process cannot be effectively bonded (wafer stress induce wafer edge bonding fail), metal diffusion (Cu diffuse issue), etc. How to solve these problems is the current wafer level Cu-Cubonding main problems faced

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