A Coarse-Grained Reconfigurable Array Circuit Based on Auto-routing Interconnect Network

Abstract

The invention provides an array circuit with reconfigurable coarsness on the basis of an automatic wiring interconnection network. The array circuit comprises a plurality of processing unit clusters and an inter-cluster interconnection network, wherein each processing unit cluster comprises a plurality of processing units and is used for distributing data input into the processing unit cluster to the corresponding processing unit for processing and outputting a processing result of the processing unit; the inter-cluster interconnection network is used for exchanging data among all processing units; and the processing unit cluster also comprises an inner interconnection network which is used for exchanging data among the processing units in the processing unit cluster and distributing the input data from other processing unit clusters to the corresponding processing unit.

Description

technical field [0001] The invention relates to the technical field of embedded reconfigurable computing structures, in particular to a coarse-grained reconfigurable array circuit based on an automatic wiring interconnection network. Background technique [0002] Traditionally, there are two ways to implement an algorithm, one is through an application-specific integrated circuit in the form of a hardware circuit, and the other is through a general-purpose processor in the form of an instruction stream. The former has high performance but low functional flexibility, and the latter is just the opposite, low performance but high functional flexibility. A reconfigurable structure is a structure that can combine the advantages of the two, which has both high performance and moderate functional flexibility. According to the granularity of reconfiguration, reconfigurable structures can be divided into coarse-grained reconfigurable structures and fine-grained reconfigurable struct...

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Problems solved by technology

[0007] (2) CGRA based on the network topology in the form of a two-dimensional grid plus the global MIN can guarantee the connection of any pair of PEs, but at the cost of increasing area overhead and power consumption, and reducing the maximum operating frequency

Therefore, compared with CGRA based on the interconnection network topology in the form of a two-dimensional grid, this structure will increase: Log 2 Area overhead of N×N / 2 two-input / two-output Crossbars, Log 2 N-level path delay and Log 2 Dynamic power consumption caused by the flipping of N×N interconnect lines

[0009] (3) The input selector contained in the PE of the existing CGRA is large in size, requires more configuration information, and there is waste in operand selection

Each PE contains two input selectors of the same size, and the ALU inside the PE only needs two operands, so there is a waste of operand selection

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