Array substrate and liquid crystal display panel
An array substrate and matrix arrangement technology, which is applied in the field of liquid crystal displays, can solve problems such as uneven surface of the film layer, and achieve the effects of good flatness, elimination of adverse effects, and improvement of light leakage problems.
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Embodiment 2
[0037] First introduce the array substrate corresponding to mid-com.
[0038] See figure 1 This figure is a cross-sectional view of an embodiment of the array substrate provided by the present invention.
[0039] The array substrate provided by this embodiment further includes: a first insulating layer 208, a pixel electrode layer 210, and a common electrode layer 209;
[0040] In addition, the array substrate further includes: a substrate 201, a gate 202, a gate insulating layer 203, and a semiconductor 204.
[0041] The common electrode layer 209 is located on the second flat layer 206b, the common electrode layer 209 includes a plurality of mutually independent touch electrodes, and each of the touch electrodes is connected to one or more touch electrodes. Line 207;
[0042] The first insulating layer 208 is located on the common electrode layer 209;
[0043] The pixel electrode layer 210 is located on the first insulating layer 208.
[0044] A metal pad 207a disposed on the first fla...
Embodiment 3
[0055] For details, see figure 2 As shown, this embodiment and figure 1 The difference in the illustrated embodiment is that figure 1 In the middle, the drain of the thin film transistor is indirectly electrically connected to the pixel electrode layer through two vias. In this embodiment, the drain of the thin film transistor is directly electrically connected to the pixel electrode layer through a via hole. When only one via hole is used for electrical connection, the penetration depth of the hole needs to be relatively deep, and the process is more complicated.
[0056] Such as figure 2 As shown, in this embodiment, a third via hole 213 penetrating through the first flat layer 206a and the second flat layer 206b is provided above the drain electrode 205 of the thin film transistor, and the pixel electrode layer 210 passes through the third via hole. The hole 213 is connected to the drain electrode 205 of the thin film transistor.
[0057] Array substrate embodiment four:
[005...
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