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Method for constructing UVM verification component by utilizing existing Verilog BFM

A component and structure technology, applied in the field of computer structure verification, to save time and shorten the verification cycle

Active Publication Date: 2015-03-25
SHANDONG LANGCHAO YUNTOU INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present invention aims at the deficiencies and problems existing in the prior art, and in order to solve the problem of reusing the previous Verilog bus function model BFM in the UVM environment when migrating from a Verilog-based verification environment to a UVM verification environment, it provides a method that utilizes the existing Verilog BFM Method for Constructing UVM Verification Components

Method used

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  • Method for constructing UVM verification component by utilizing existing Verilog BFM
  • Method for constructing UVM verification component by utilizing existing Verilog BFM
  • Method for constructing UVM verification component by utilizing existing Verilog BFM

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Embodiment Construction

[0018] Below in conjunction with accompanying drawing description.

[0019] Such as figure 1 , the middle is the logical description of the circuit under test, the left is the bus model BFM generated by the stimulus, and the right is the bus model BFM for response detection. Whether it is a stimulus generation or a response detection model, it is generally packaged in a Verilog module. In the module, various stimuli are generated or various responses are collected through functions or tasks to simulate external devices of the circuit under test. The three parts are instantiated in the top level and connected to each other. A sample program is:

[0020]

[0021] Such as figure 2 , the left side of the picture is the object under test (DUT) in the UVM verification platform. The middle part is the environment subject uvm env, which includes multiple entities uvm agent. Each uvm agent includes a sequencer, a driver, and a monitor. Each uvm agent is connected to the objec...

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Abstract

The method discloses a method for constructing a UVM verification component by utilizing an existing Verilog BFM and belongs to the field of computer construction verification. The method comprises the steps that the existing Verilog BFM is transformed; the transformed Verilog BFM is integrated into a UVM verification environment. According to the method, the existing bus model can be used in the new UVM environment without too much modification, so that existing resources are effectively utilized, the number of codes needing to be modified is the smallest, the time is saved to the maximum degree, the verification cycle is greatly shortened, and the situation that errors caused by a verification platform itself affect verification progress is avoided.

Description

technical field [0001] The invention discloses a method for constructing a UVM verification component, which belongs to the field of computer construction verification, and specifically relates to a method for constructing a UVM verification component by utilizing an existing Verilog BFM. Background technique [0002] Verilog is a hardware description language widely used in FPGA and digital ASIC design, using it to describe digital logic circuits, and using it to describe circuit peripherals to build a simulation platform. The early bus functional model BFM (bus functional model) is a model of circuit peripherals constructed by engineers using hardware description languages ​​such as Verilog to generate various stimuli to drive the model of the designed circuit, and to detect the output of the circuit to judge the circuit function as expected. [0003] With the development of digital circuit technology, the traditional Verilog language can no longer meet the needs of build...

Claims

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Application Information

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IPC IPC(8): G06F11/26
Inventor 耿介于治楼毕研山
Owner SHANDONG LANGCHAO YUNTOU INFORMATION TECH CO LTD
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