Breakdown-preventing SOI folding gate insulated tunneling bipolar transistor and making method thereof

A bipolar transistor and gate insulation technology, which is applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as the inability to substantially improve the tunneling probability of silicon materials, increase in static power consumption, and increase process difficulty.

Inactive Publication Date: 2015-03-11
SHENYANG POLYTECHNIC UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, the continuous shortening of the channel length has led to an increase in the subthreshold swing of MOSFETs, which has resulted in severe degradation of switching characteristics and a significant increase in static power consumption.
Although the degradation of device performance can be alleviated by improving the gate electrode structure, when the device size is further reduced to below 20 nanometers, even with the optimized gate electrode structure, the subthreshold swing of the device will also decrease. increases with further reductions in the device channel length, resulting in further deterioration of the device performance
[0003] Tunneling Field Effect Transistors (TFETs), compared with MOSFETs, although its average subthreshold swing has been improved, but its forward conduction current is too small. Narrow materials are used to generate the tunneling part of the tunneling field effect transistor, which can increase the tunneling probability to improve the transfer characteristics, but increases the difficulty of the process
In addition, the use of high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot substantially increase the tunneling probability of the silicon material, so For the transfer characteristics of tunneling field effect transistors, the improvement is very limited

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  • Breakdown-preventing SOI folding gate insulated tunneling bipolar transistor and making method thereof
  • Breakdown-preventing SOI folding gate insulated tunneling bipolar transistor and making method thereof
  • Breakdown-preventing SOI folding gate insulated tunneling bipolar transistor and making method thereof

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Embodiment Construction

[0084] Below in conjunction with accompanying drawing, the present invention will be further described: figure 1 It is a schematic diagram of a three-dimensional structure of an anti-breakdown SOI folded gate insulated tunneling bipolar transistor formed on an SOI substrate in the present invention; figure 2 A schematic diagram of a three-dimensional structure after peeling off the blocking insulating layer 11 for the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention; image 3 A schematic diagram of a three-dimensional structure after peeling off the emitter 9, the collector 10 and the blocking insulating layer 11 for the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention; Figure 4 A schematic diagram of a three-dimensional structure after peeling off the emitter 9, the collector 10, the blocking insulating layer 11 and the folded gate electrode 8 for the anti-breakdown SOI folded gate i...

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Abstract

The invention relates to a breakdown-preventing SOI (Silicon on Insulator) folding gate insulated tunneling bipolar transistor. In contrast with the same size of MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) or tunneling filed effect transistor, the forward and reverse breakdown-preventing capability of a device in a deep nanoscale is obviously improved through introducing a low impurity concentration of breakdown protection zones in a collector junction and an emitter junction. Insulated tunneling structures are simultaneously arranged on the two sides and the upper surface of a base region, and insulated tunneling effects are simultaneously generated on the two sides and the upper surface of the base region under the control action of gate electrodes, so that the tunneling current generating rate is improved. Excellent switching on / off properties are realized through utilization of an extremely sensitive correlation between the resistance of a tunneling insulating layer and field strength in the tunneling insulating layer. Excellent forward conducting properties are realized through enhancing a tunneling signal by an emitter. Besides, the invention further provides a specific making method of the breakdown-preventing SOI folding gate insulated tunneling bipolar transistor and an array thereof. The transistor obviously improves the work properties of a nanoscale integrated circuit unit and is suitable for being popularized and applied.

Description

Technical field: [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a structure of an anti-breakdown SOI folded-gate insulated tunneling bipolar transistor suitable for the manufacture of high-performance ultra-high-integrated integrated circuits. The specific manufacturing method of the pole transistor array. Background technique: [0002] At present, with the continuous improvement of the integration level, the source electrode and the channel or between the drain electrode and the channel of the integrated circuit unit Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) devices form a steep mutation PN within a few nanometers. Junction, when the drain-source voltage is large, this steep abrupt PN junction will have a breakdown effect, which will cause the device to fail. As the size of the device continues to shrink, this breakdown effect becomes more and more obvious. In addition, the continuous shorte...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/739H01L29/10H01L21/331
CPCH01L29/0603H01L29/66325H01L29/739
Inventor 靳晓诗吴美乐刘溪揣荣岩
Owner SHENYANG POLYTECHNIC UNIV
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