High-resistance silicon substrate based LDMOS MMIC chip

Abstract

The invention discloses a high-resistance silicon substrate based LDMOS MMIC chip. An LDMOS transistor, an inductor, a capacitor, a resistor, metal connection lines, a graph and a soldering pad are integrated on the chip. The chip is characterized in that a P-type high-resistance silicon substrate without epitaxial layers is used; an LDMOS source electrode in the front of the chip is connected with a metal layer at the back of the chip through a silicon substrate through hole technology. The chip has the advantages that the high-resistance silicon substrate is used, and the DMOS source electrode in the front of the chip is connected with the metal layer at the back of the chip through the silicon substrate through hole technology; by means of the high-resistance silicon substrate, the to-earth parasitic capacitance and consumption of the inductor, the capacitor, the resistor, the metal connection lines, the graph, the soldering pad and the like on the chip is reduced, the LDMOS MMIC performance is improved, and accordingly, metal inter-connection layers are reduced, and the cost is reduced. Meanwhile, the PN-junction capacitance between the LDMOS transistor N-type drain electrode and drift region and the P-type substrate can be reduced, so that the LDMOS transistor output capacitance is reduced, and the LDMOS apparatus bandwidth and power conversion efficiency is improved.

Description

technical field [0001] The invention relates to an LDMOS MMIC chip based on a high-resistance silicon substrate, belonging to the technical field of LDMOS devices. Background technique [0002] In LDMOS devices, there is a large current between the source and the ground on the back of the chip. In order to reduce the resistance between the source and the ground, a low-resistance heavily doped P-type substrate is usually used, and a low-resistance P-type silicon layer is epitaxially grown on it, and an LDMOS device is fabricated in the epitaxial layer. [0003] LDMOS-based MMIC (Monolithic Microwave Integrated Circuit) needs to integrate passive components such as inductors, capacitors, and resistors on the chip. However, the isolation between the low-resistance and heavily doped P-type substrate and the top-layer metal as the ground does not exceed 10um, resulting in a large parasitic capacitance between the ground and the ground, which seriously reduces the Q and self-reso...

AI Technical Summary

Problems solved by technology

However, the isolation between the low-resistance and heavily doped P-type substrate and the top-layer metal as the ground does not exceed 10um, resulting in a large parasitic capacitance between the ground and the ground, which seriously reduces the Q and self-resonant frequency of the inductor and increases the Parasitic capacitance to ground of capacitors, resistors, metal wiring, patterns and pads, etc., degrades the performance of LDMOS MMIC

In order to reduce the parasitic capacitance between metal wiring and graphics, inductors, capacitors, resistors and other passive components and pads and ground, multi-layer metal interconnection technology (more than 4 layers of metal) is usually used to increase metal wiring and graphics, inductance, Isolation between passive components such as capacitors, resistors and pads and ground, but increases the cost

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