Clock transfer circuit, video processing system, and semiconductor integrated circuit

Abstract

A clock transfer circuit receives input data synchronized with a first clock and outputs the received input data as output data synchronized with a second clock having a different frequency. A write address control unit (23) operates in synchronization with the first clock and supplies a write address to a memory (21). A read address control circuit (24) operates in synchronization with the second clock and supplies a read address to the memory (21). A frequency comparator (30) compares the input data with the output data in the frequency of a predetermined event. Based on this comparison result, clock adjustment units (14, 15) adjust the frequency of the second clock.

Description

Technical field [0001] The present invention relates to a clock conversion circuit that converts data input in synchronization with a clock into clocks of different cycles for output. Background technique [0002] The clock conversion circuit converts the data input in synchronization with the clock into clocks of different cycles for output. The clock conversion circuit uses, for example, a 2-port RAM to control the write address and the read address at an appropriate distance to convert the write data into clocks of different cycles, read them out, and transmit them. [0003] Here, if the interval between the write address and the read address becomes narrower, they will compete with each other, which may cause a so-called memory control address flaw. In the prior art, in order to prevent address contention, the write address and the read address are compared, and the address is reset when the gap between the addresses is narrow and contention is required. [0004] In Patent Docu...

AI Technical Summary

Problems solved by technology

[0003] Here, if the interval between the write address and the read address is narrowed sequentially, they will compete with each other, causing a so-called flaw in the memory control address.

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