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Device backboard high-speed bus link layer communication protocol based on M-LVDS

A high-speed bus and communication protocol technology, applied in the bus network, data exchange through path configuration, electrical components, etc., can solve problems such as mismatching bus design requirements, low stability and reliability, and bus failure , to achieve the effect of improving signal integrity, improving system stability, and meeting high real-time performance

Active Publication Date: 2015-02-04
GUODIAN NANJING AUTOMATION SOFTWARE ENG
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Problems solved by technology

It does not match the bus design requirements of multi-master peering (meaning that a bus has multiple master nodes to send resources equally, that is, each node can actively trigger information sending on an equal basis), the bus flexibility is low, and once the master node is abnormal, the entire The bus will not work properly, the stability and reliability will not be high

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  • Device backboard high-speed bus link layer communication protocol based on M-LVDS
  • Device backboard high-speed bus link layer communication protocol based on M-LVDS
  • Device backboard high-speed bus link layer communication protocol based on M-LVDS

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Embodiment Construction

[0034] The present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0035] Such as figure 1 As shown, an M-LVDS-based device backplane high-speed bus link layer communication protocol. The M-LVDS-based device backplane high-speed bus uses differential signals from an interface chip that supports M-LVDS level standards to build a bus peripheral hardware loop. Interface chip (attached figure 1 The single-ended input and separate output of several modules in the) are connected to FPGA, and the bus link layer communication protocol control is realized by FPGA.

[0036] The high-speed bus on the backplane of the device adopts variable data bit width control to realize communication bandwidth configuration; it can be configured as 1-wire, 2-wire, 4-wire, 8-wire mode, which can realize 80Mbps, 160Mbps, 320Mbps, 640Mbps communication bandwidth respectively , It can also be configured with a bit width of 16-line and 32-line to ac...

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Abstract

The invention discloses a device backboard high-speed bus link layer communication protocol based on M-LVDS, adopting the variable data bit wide design, being suitable for large data volume communication of different data bandwidth requirement, adopting collision detection and lossless arbitration to compete for speaking right, adopting the priority rotate method for guaranteeing roll polling speak for each node, preventing occupying the bus for some node for a long time and supporting the hot plug function, the normal communication of other nodes on the bus is not impacted while any abnormal node drops out, the stability and reliability are high. The bus physical layer adopts M-LVDS with high-level ESD protection function, the reflection and EMI can be reduced by controlling the slew rate, the signal integrity is raised for greatly raising the system stability. The device backboard high-speed bus link layer communication protocol based on M-LVDS is used for realizing the industrial control, relay protection and high speed peer data interaction among modules in the safe automatic device, and satisfying the high real time performance, high reliability, flexible and extensible performance requirement to the protection control system for the intelligent power grid.

Description

Technical field [0001] The invention relates to the high-speed backplane transmission bus field of a smart grid front information processing module, and specifically provides an M-LVDS-based device backplane high-speed bus link layer communication protocol. Background technique [0002] Smart grid protection and control devices need to access a large number of digital signals, limited to the number of single-module interfaces and limited processing capabilities, and need to be processed by multiple pre-information processing modules and then collected into a single or multiple CPU modules for algorithm and logic operation. Therefore, a high-speed backplane transmission bus is needed to communicate large amounts of data between modules in the device. [0003] Existing high-speed backplane buses such as PCI and VME adopt a parallel bus mode, which has disadvantages such as many backplane connections, complicated design, high cost, poor anti-interference ability, and complicated cont...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/40H04L29/06
Inventor 叶品勇余华武陈新之陈庆旭丁毅肖文
Owner GUODIAN NANJING AUTOMATION SOFTWARE ENG
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