Fault-tolerant method aiming at TSV fault grading in 3D NoC

Abstract

The invention discloses a fault-tolerant method aiming at TSV (Through Silicon Via) fault grading in 3D NoC (Network on Chip). According to the method, TSVs and data bits are respectively divided into four groups; if a TSV fault state value is within 6, the serial transmission among the groups and among data bits in the groups can be realized by using rest available TSVs; and otherwise, a localized fault-tolerant routing algorithm is used, and the address of the optimum TSV is found out from a locally stored TSV state table and is used as a temporary target address to be added to a data packet header for completing interlayer communication. According to the scheme of the method provided by the invention, the corresponding fault-tolerant method is selected through judging the fault grade of TSV links; higher reliability of the system is ensured; and meanwhile, the waste of available resources is reduced.

Description

technical field [0001] The invention relates to the technical field of application of integrated circuit chips, in particular to a fault tolerance method for TSV fault classification in 3D NoC. Background technique [0002] 3D IC technology is to stack multiple layers of silicon chips together through short and dense Through Silicon Via (TSV), which shortens the link length and increases link bandwidth, thereby improving network performance and reducing communication delay. It has been widely used in the semiconductor industry. Get considerable income. Although the use of 3D Network on Chip (NoC) architectures in integrated systems has many advantages over traditional 2D NoCs, there are several factors that can cause 3D architectures to become non-fully interconnected. The reason can be divided into two aspects: [0003] 1. Non-full interconnection caused by TSV failure. During the packaging process of 3D IC, due to the possibility of voids or air bubbles during the m...

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Problems solved by technology

[0003] 1. Non-full interconnection caused by TSV failure

In the packaging process of 3D IC, due to the possibility of voids or air bubbles during the manufacture of TSVs, TSVs and pads do not coincide during bonding, and short circuits between TSVs or open circuits between TSVs and pads during soldering will cause TSV failures

At the same time, TSV is also prone to failure during use

[0004] 2. In some specific applications, the size of each module is different (the area of ​​an IP core in the upper layer is equivalent to the total area of ​​several IP cores in the lower layer, and the IP core in the upper layer is only connected to one IP core in the lower layer through TSV), resulting in 3D NoC is not fully interconnected

[0006] 1. Using redundant TSVs, in order to achieve a certain fault tolerance, it is necessary to add enough redundant TSVs, which brings a large area and power consumption overhead, and can only accommodate a limited number of TSV failures

[0007] 2. Reinforce the TSV. When the TSV link fails, use the remaining available TSV in the link to transmit data serially, reducing the system performance degradation caused by TSV failure, but without adding redundant TSV Fault tolerance is not high

[0008] 3. Use fault-tolerant routing algorithm to bypass faulty nodes, but this method will increase delay and power consumption and decrease system performance, and will cause waste of non-faulty resources in some systems

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