Reconfigurable rapid parallel multiplier

A multiplier and fast technology, applied in the field of fast parallel multipliers, can solve problems such as long calculation time and unsuitable for high-speed applications, and achieve the effect of reducing calculation time

Inactive Publication Date: 2014-07-23
HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, this structure requires O(m 2 ) space complexity and usually O(m) time delay
Bit-parallel array multipliers req

Method used

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] Use attached figure 1 The shown multi-way KA (Karatsuba Algorithm) and (b, 2)-way BKA (Bivariate Karatsuba Algorithm) algorithm to obtain GF(2 m ) on a reconfigurable multiplier, where the elements on the domain are represented by SPB (Shifted polynomial basis). Set the element on the domain Can be expressed as A=A 0 +A 1 x n +A 2 x 2n ,in

[0022] and A i =a i，0 +a i，1 x+...a i，n-1 x n-1 , 0≤j≤n-1. Let GF(2 m ) consists of an irreducible polynomial F(x) of degree m. For A, B∈GF(2 m ), product C=x -v ABmodF(x) can be expressed as:

[0023] C=x -v [A 0 B 0 +(A 0 B 0 +A 1 B 1 +A 01 B 01 )x n +(A 0 B 0 +A 1 B 1 +A 2 B 2 +A 02 B 02 )x 2n +(A 1 B 1 +A 2 B 2 +A 12 B 12 )X 3n +A 2 B 2 x 4n ]modF(x)=x -v [A 0 B 0 (1+x n +x 2n )+A 1 B 1 (x n +x 2n +x 3n )+A 2 B 2 (x 2n +x 3n +x 4n...

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Abstract

The invention provides a reconfigurable rapid parallel multiplier. The reconfigurable rapid parallel multiplier comprises a control unit, a transient memory, two reconfigurable decomposition operand generating circuits, a secondary polynomial multiplier, a frequency adjustment circuit and an FPR circuit, wherein the control unit outputs a control vector S0, a control vector S1 and a control vector S2, the control vector S0 and the control vector S1 are used for controlling the two reconfigurable decomposition operand generating circuits so that i and i can be generated in the same way, the secondary polynomial multiplier is used for generating a control vector S2 which is used for controlling the frequency adjustment circuit to generate a D stored in the transient memory, i=0, 1, ..., and 5, and the FPR circuit is used for generating a final result C. Compared with an existing multiplier, the expandable multiplier has the advantages that the calculation time is shortened obviously, the area, the ADP and the power consumption are reduced obviously, and an analysis result provides a valuable reference for carrying out a pairing algorithm and an elliptic curve digital signature algorithm on an embedded system with limited resources and a smart phone.

Description

technical field [0001] The invention belongs to the field of encryption processing and relates to a reconfigurable fast parallel multiplier. Background technique [0002] Finite field multiplication is widely used in encryption algorithms and error control coding. For cryptographic applications, such as Diffie-Hellman key exchange, digital signatures, ECC and pairwise encryption all use finite field multiplication. SPB (Shifted Polynomial Basis, shifted polynomial basis) has some advantages in the implementation of finite field multiplication. For pair encryption applications, Weil and Tate pairing based on ECC algorithm requires a large number of extended operations on finite fields. For example, by calculating the definition in the compound domain GF(2 4×12222 The Tate pairing of a prime number elliptic curve on ) can achieve the security of 128-bit symmetric key. Therefore, it is important for the design of efficient hardware multiplication over large finite fields, w...

Claims

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Application Information

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IPC IPC(8): G06F7/52
Inventor 潘正祥杨春生李瑶李秋莹闫立军蔡正富
Owner HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL
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