Full parallel input quasi-cyclic matrix multiplier based on ring shift left in CMMB

Abstract

The invention provides a full parallel input quasi-cyclic matrix multiplier based on ring shift left in a CMMB, wherein the multiplier is used for achieving multiplication of vectors m and quasi-cyclic matrixes F in CMMB standard multiple rate QC-LDPC approximate lower triangular codes. The multiplier comprises five generator polynomial lookup tables for prestoring all circulant matrix generator polynomials in matrixes F, five 256-bit binary multipliers for carrying out scalar multiplying on vector fields of the m and generator polynomial bits, 256 6-bit binary adders for carrying out modulor-2 addition on products and shifting register content, and a 256-bit shifting register for storing the sum of results obtained after 1-bit ring shift left is carried out. The full parallel input multiplier is compatible with all code rates and has the advantages that the number of the registers is small, power consumption is little, cost is low, work frequency is high and the handling capacity is large.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a cyclic left-shift quasi-circular matrix multiplier with full parallel input in CMMB standard multi-code rate QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulatory matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit; the first column of the circulatory matrix is ​​the result of the cyclic shift of the last column by 1 bit, and the remaining columns ...

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Problems solved by technology

[0022] In order to be compatible with two kinds of code rates, the existing solution of the quasi-circular matrix multiplier with full parallel input in the CMMB standard multi-code rate QC-LDPC approximate lower triangular coding has two disadvantages: one is that 1280 registers are required, which leads to the power of the circuit High consumption and high cost; the second is that the modulo 2 adder has 1280 input terminals, and the delay of the addition operation is long, which will result in low operating frequency and low throughput of the multiplier

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