Power management chip with test mode

Abstract

The invention discloses a power management chip with a test mode, and belongs to the technical field of electronic circuits. The power management chip with the test mode comprises an output pin, a function circuit connected with the output pin and a detection circuit connected with the output end of the function circuit, and the detection circuit determines whether the power management chip needs to enter in the test mode or not based on the voltage on the output pin. The detection circuit compares the voltage on the output pin with a threshold voltage, when the voltage on the output pin is larger than the threshold voltage, a valid test mode signal is output, and otherwise the detection circuit outputs an invalid test mode signal. Through the multiplex reset output pin, the power management chip is tested when a reset circuit of the PMU is in a non-work state, the number of pins is reduced, and the test function can also be achieved on the premise of not increasing the packaging size.

Description

technical field [0001] The invention discloses a power management chip with a test mode, which belongs to the technical field of electronic circuits. Background technique [0002] In the prior art, the power management chip usually uses an independent pin to set the test mode. When the pin is connected to the power supply, the power management chip enters the test mode; when the pin is grounded, the power management chip enters the normal working mode. For example, in the wafer test of the chip (before packaging, including the steps of screening out bad chips and adjusting important parameters), by setting the circuit to enter the test mode, it is helpful to test some parameters that cannot be tested when the chip is working normally. Realize monitoring or greatly reduce test time (in order to test certain parameters, it may be necessary to wait for example 1 second under normal working conditions, and generally a waiting time of more than 100 milliseconds cannot be tolerat...

AI Technical Summary

Problems solved by technology

For example, in the wafer test of the chip (before packaging, including the steps of screening out bad chips and adjusting important parameters), by setting the circuit to enter the test mode, it is helpful to test some parameters that cannot be tested when the chip is working normally. Realize monitoring or greatly reduce test time (in order to test certain parameters, it may be necessary to wait for example 1 second under normal working conditions, and generally a waiting time of more than 100 milliseconds cannot be tolerated during wafer testing because the time cost is too high)

But for the case where the package pins are tight, increasing the pins will increase the package size, which will increase the size of the printed circuit board, which is not conducive to miniaturization design; at the same time, a larger package means higher packaging cost

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