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NCS algorithm parallelization method based on multiple FPGA platforms

An algorithm and platform technology, applied in the field of parallelization of NCS algorithms, can solve the problems of low computing efficiency, high memory read speed and high processor performance requirements, and achieve the effect of improving efficiency

Inactive Publication Date: 2014-05-21
NANJING UNIV +1
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Problems solved by technology

However, the computing efficiency of the existing NCS algorithm on-chip software is low, and the reading speed of the memory and the performance of the processor are high.

Method used

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  • NCS algorithm parallelization method based on multiple FPGA platforms
  • NCS algorithm parallelization method based on multiple FPGA platforms
  • NCS algorithm parallelization method based on multiple FPGA platforms

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Embodiment Construction

[0022] The solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0023] This embodiment is based on a multi-FPGA platform composed of 4 Xilinx XC6VLX550T FPGA chips, such as figure 1 As shown, each FPGA chip is designed with a heterogeneous multi-core prototype chip based on 4*4 2D mesh architecture, the data bit width is 64 bits, and the 4*4 2D mesh architecture is expanded to 16*16 2D mesh through the high-speed channel between FPGAs architecture. Each FPGA chip integrates 4 computing cluster units and 1 transposition cluster unit to complete a large number of calculations and transpositions in the NCS algorithm. The overall software flow of the NCS algorithm is as follows: figure 2 shown. In the following, combined with the NCS algorithm, taking an image scale with a data volume of 32M Byte as an example, the pipeline method and task parallelization method will be described in detail.

[0024] The method fo...

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Abstract

The invention relates to an NCS algorithm parallelization method based on multiple FPGA platforms. The method includes the steps of subaperture processing and synthetic aperture processing, and the subaperture processing and the synthetic aperture processing are carried out in a paralleled mode through two-stage assembly lines. A pipelining paralleled processing mode is adopted in the subaperture processing. A plurality of data processing tasks independent from one another in the subaperture processing and the synthetic aperture processing are allocated in a plurality of chips for paralleled execution. The NCS algorithm parallelization method based on the multiple FPGA platforms has the advantages that a multi-core hardware architecture is utilized to divide operating tasks into a plurality of sub-tasks and the sub-tasks are allocated to processing units of different chips for being processed respectively, so parallelization of task processing is achieved, and the efficiency of on-chip software is effectively improved.

Description

technical field [0001] The invention relates to a method for parallelizing NCS algorithms, in particular to a method for parallelizing NCS algorithms based on multiple FPGA platforms. Background technique [0002] Synthetic Aperture Radar (SAR) imaging has been widely used in various fields of national economy and military. Conventional SAR imaging algorithms include RD algorithm and CS algorithm, etc., but the RD algorithm is difficult to meet the radar imaging requirements for large scenes with high resolution requirements and large squint angles, while the CS algorithm will cause large scatter in the case of large oblique angles of view. Focus, so the NCS algorithm came into being on this basis. The efficiency of traditional serial algorithms is relatively low, and it is difficult to meet the requirements of real-time imaging. The NCS algorithm that introduces the sub-aperture structure can better adapt to larger oblique viewing angles, and can more easily parallelize t...

Claims

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Application Information

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IPC IPC(8): G06F15/16G06F9/46
Inventor 潘红兵钱禹李丽郑昱李磊余慧徐峰黄炎
Owner NANJING UNIV
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